| Message ID | 20220407113703.26423-2-allen-kh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mt8192: Add mmc device nodes | expand |
Il 07/04/22 13:37, Allen-KH Cheng ha scritto: > In mt8192 SoC, mmc driver dose not use the MSDC module to control > clock. It will read/write register to enable/disable clock. Also > there is no other device of mt8192 using MSDC controller. > > We add mmc nodes for mt8192 SoC and remove the clock-controller in > dts for avoid a duplicate unit-address(11f60000) warning. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On Thu, Apr 07, 2022 at 07:37:03PM +0800, Allen-KH Cheng wrote: > In mt8192 SoC, mmc driver dose not use the MSDC module to control > clock. It will read/write register to enable/disable clock. Also > there is no other device of mt8192 using MSDC controller. > > We add mmc nodes for mt8192 SoC and remove the clock-controller in > dts for avoid a duplicate unit-address(11f60000) warning. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++--- > 1 file changed, 30 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index a6da7b04b9d4..18a58239d6f1 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -985,10 +985,36 @@ > #clock-cells = <1>; > }; > > - msdc: clock-controller@11f60000 { > - compatible = "mediatek,mt8192-msdc"; > - reg = <0 0x11f60000 0 0x1000>; > - #clock-cells = <1>; > + mmc0: mmc@11f60000 { > + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, > + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, > + <&msdc_top CLK_MSDC_TOP_SRC_0P>, > + <&msdc_top CLK_MSDC_TOP_P_CFG>, > + <&msdc_top CLK_MSDC_TOP_P_MSDC0>, > + <&msdc_top CLK_MSDC_TOP_AXI>, > + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; > + clock-names = "source", "hclk", "source_cg", "sys_cg", > + "pclk_cg", "axi_cg", "ahb_cg"; > + status = "disabled"; > + }; > + > + mmc1: mmc@11f70000 { > + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, > + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, > + <&msdc_top CLK_MSDC_TOP_SRC_1P>, > + <&msdc_top CLK_MSDC_TOP_P_CFG>, > + <&msdc_top CLK_MSDC_TOP_P_MSDC1>, > + <&msdc_top CLK_MSDC_TOP_AXI>, > + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; > + clock-names = "source", "hclk", "source_cg", "sys_cg", > + "pclk_cg", "axi_cg", "ahb_cg"; > + status = "disabled"; > }; > > mfgcfg: clock-controller@13fbf000 { > -- > 2.18.0 > >
On 07/04/2022 13:37, Allen-KH Cheng wrote: > In mt8192 SoC, mmc driver dose not use the MSDC module to control > clock. It will read/write register to enable/disable clock. Also > there is no other device of mt8192 using MSDC controller. > > We add mmc nodes for mt8192 SoC and remove the clock-controller in > dts for avoid a duplicate unit-address(11f60000) warning. > Applied, thanks! Matthias > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++--- > 1 file changed, 30 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index a6da7b04b9d4..18a58239d6f1 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -985,10 +985,36 @@ > #clock-cells = <1>; > }; > > - msdc: clock-controller@11f60000 { > - compatible = "mediatek,mt8192-msdc"; > - reg = <0 0x11f60000 0 0x1000>; > - #clock-cells = <1>; > + mmc0: mmc@11f60000 { > + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, > + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, > + <&msdc_top CLK_MSDC_TOP_SRC_0P>, > + <&msdc_top CLK_MSDC_TOP_P_CFG>, > + <&msdc_top CLK_MSDC_TOP_P_MSDC0>, > + <&msdc_top CLK_MSDC_TOP_AXI>, > + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; > + clock-names = "source", "hclk", "source_cg", "sys_cg", > + "pclk_cg", "axi_cg", "ahb_cg"; > + status = "disabled"; > + }; > + > + mmc1: mmc@11f70000 { > + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, > + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, > + <&msdc_top CLK_MSDC_TOP_SRC_1P>, > + <&msdc_top CLK_MSDC_TOP_P_CFG>, > + <&msdc_top CLK_MSDC_TOP_P_MSDC1>, > + <&msdc_top CLK_MSDC_TOP_AXI>, > + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; > + clock-names = "source", "hclk", "source_cg", "sys_cg", > + "pclk_cg", "axi_cg", "ahb_cg"; > + status = "disabled"; > }; > > mfgcfg: clock-controller@13fbf000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a6da7b04b9d4..18a58239d6f1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -985,10 +985,36 @@ #clock-cells = <1>; }; - msdc: clock-controller@11f60000 { - compatible = "mediatek,mt8192-msdc"; - reg = <0 0x11f60000 0 0x1000>; - #clock-cells = <1>; + mmc0: mmc@11f60000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, + <&msdc_top CLK_MSDC_TOP_SRC_0P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC0>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status = "disabled"; + }; + + mmc1: mmc@11f70000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, + <&msdc_top CLK_MSDC_TOP_SRC_1P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC1>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status = "disabled"; }; mfgcfg: clock-controller@13fbf000 {
In mt8192 SoC, mmc driver dose not use the MSDC module to control clock. It will read/write register to enable/disable clock. Also there is no other device of mt8192 using MSDC controller. We add mmc nodes for mt8192 SoC and remove the clock-controller in dts for avoid a duplicate unit-address(11f60000) warning. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++--- 1 file changed, 30 insertions(+), 4 deletions(-)