| Message ID | 20220419180938.19397-4-y.oudjana@protonmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dt-bindings: arm: mediatek: Convert some docs to DT schema | expand |
On Tue, 19 Apr 2022 22:09:39 +0400, Yassine Oudjana wrote: > From: Yassine Oudjana <y.oudjana@protonmail.com> > > Convert infracfg bindings to DT schema format. Not all drivers > currently implement resets, so #reset-cells is made a required > property only for those that do. Using power-controller in the > example node name makes #power-domain-cells required causing > a dt_binding_check error. To solve this, the node is renamed to > syscon@10001000. > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> > --- > .../arm/mediatek/mediatek,infracfg.txt | 42 ---------- > .../arm/mediatek/mediatek,infracfg.yaml | 79 +++++++++++++++++++ > 2 files changed, 79 insertions(+), 42 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/ infracfg@10001000: '#reset-cells' is a required property arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtb arch/arm64/boot/dts/mediatek/mt7986b-rfb.dtb syscon@10001000: '#reset-cells' is a required property arch/arm64/boot/dts/mediatek/mt2712-evb.dtb
On 19/04/2022 20:09, Yassine Oudjana wrote: > From: Yassine Oudjana <y.oudjana@protonmail.com> > > Convert infracfg bindings to DT schema format. Not all drivers > currently implement resets, so #reset-cells is made a required > property only for those that do. Using power-controller in the > example node name makes #power-domain-cells required causing > a dt_binding_check error. To solve this, the node is renamed to > syscon@10001000. > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> > --- > .../arm/mediatek/mediatek,infracfg.txt | 42 ---------- > .../arm/mediatek/mediatek,infracfg.yaml | 79 +++++++++++++++++++ > 2 files changed, 79 insertions(+), 42 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > deleted file mode 100644 > index f66bd720571d..000000000000 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > +++ /dev/null > @@ -1,42 +0,0 @@ > -Mediatek infracfg controller > -============================ > - > -The Mediatek infracfg controller provides various clocks and reset > -outputs to the system. > - > -Required Properties: > - > -- compatible: Should be one of: > - - "mediatek,mt2701-infracfg", "syscon" > - - "mediatek,mt2712-infracfg", "syscon" > - - "mediatek,mt6765-infracfg", "syscon" > - - "mediatek,mt6779-infracfg_ao", "syscon" > - - "mediatek,mt6797-infracfg", "syscon" > - - "mediatek,mt7622-infracfg", "syscon" > - - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" > - - "mediatek,mt7629-infracfg", "syscon" > - - "mediatek,mt7986-infracfg", "syscon" > - - "mediatek,mt8135-infracfg", "syscon" > - - "mediatek,mt8167-infracfg", "syscon" > - - "mediatek,mt8173-infracfg", "syscon" > - - "mediatek,mt8183-infracfg", "syscon" > - - "mediatek,mt8516-infracfg", "syscon" > -- #clock-cells: Must be 1 > -- #reset-cells: Must be 1 > - > -The infracfg controller uses the common clk binding from > -Documentation/devicetree/bindings/clock/clock-bindings.txt > -The available clocks are defined in dt-bindings/clock/mt*-clk.h. > -Also it uses the common reset controller binding from > -Documentation/devicetree/bindings/reset/reset.txt. > -The available reset outputs are defined in > -dt-bindings/reset/mt*-resets.h > - > -Example: > - > -infracfg: power-controller@10001000 { > - compatible = "mediatek,mt8173-infracfg", "syscon"; > - reg = <0 0x10001000 0 0x1000>; > - #clock-cells = <1>; > - #reset-cells = <1>; > -}; > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > new file mode 100644 > index 000000000000..4f43fe9f103e > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > @@ -0,0 +1,79 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MediaTek Infrastructure System Configuration Controller > + > +maintainers: > + - Matthias Brugger <matthias.bgg@gmail.com> > + > +description: > + The Mediatek infracfg controller provides various clocks and reset outputs > + to the system. Mention here the headers with clock and reset constants. The same for patches 1 and 2. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - mediatek,mt2701-infracfg > + - mediatek,mt2712-infracfg > + - mediatek,mt6765-infracfg > + - mediatek,mt6779-infracfg_ao > + - mediatek,mt6797-infracfg > + - mediatek,mt7622-infracfg > + - mediatek,mt7629-infracfg > + - mediatek,mt7986-infracfg > + - mediatek,mt8135-infracfg > + - mediatek,mt8167-infracfg > + - mediatek,mt8173-infracfg > + - mediatek,mt8183-infracfg > + - mediatek,mt8516-infracfg > + - const: syscon > + - items: > + - const: mediatek,mt7623-infracfg > + - const: mediatek,mt2701-infracfg > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +if: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt2701-infracfg > + - mediatek,mt2712-infracfg > + - mediatek,mt7622-infracfg > + - mediatek,mt7986-infracfg > + - mediatek,mt8135-infracfg > + - mediatek,mt8173-infracfg > + - mediatek,mt8183-infracfg > +then: > + required: > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + infracfg: syscon@10001000 { reset-controller or clock-controller instead, because syscon is for blocks having only the syscon function. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt deleted file mode 100644 index f66bd720571d..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ /dev/null @@ -1,42 +0,0 @@ -Mediatek infracfg controller -============================ - -The Mediatek infracfg controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt2712-infracfg", "syscon" - - "mediatek,mt6765-infracfg", "syscon" - - "mediatek,mt6779-infracfg_ao", "syscon" - - "mediatek,mt6797-infracfg", "syscon" - - "mediatek,mt7622-infracfg", "syscon" - - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt7629-infracfg", "syscon" - - "mediatek,mt7986-infracfg", "syscon" - - "mediatek,mt8135-infracfg", "syscon" - - "mediatek,mt8167-infracfg", "syscon" - - "mediatek,mt8173-infracfg", "syscon" - - "mediatek,mt8183-infracfg", "syscon" - - "mediatek,mt8516-infracfg", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The infracfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. -Also it uses the common reset controller binding from -Documentation/devicetree/bindings/reset/reset.txt. -The available reset outputs are defined in -dt-bindings/reset/mt*-resets.h - -Example: - -infracfg: power-controller@10001000 { - compatible = "mediatek,mt8173-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml new file mode 100644 index 000000000000..4f43fe9f103e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Infrastructure System Configuration Controller + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +description: + The Mediatek infracfg controller provides various clocks and reset outputs + to the system. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt6765-infracfg + - mediatek,mt6779-infracfg_ao + - mediatek,mt6797-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7629-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8167-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg + - mediatek,mt8516-infracfg + - const: syscon + - items: + - const: mediatek,mt7623-infracfg + - const: mediatek,mt2701-infracfg + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg +then: + required: + - '#reset-cells' + +additionalProperties: false + +examples: + - | + infracfg: syscon@10001000 { + compatible = "mediatek,mt8173-infracfg", "syscon"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + };