| Message ID | 20220419043348.1483625-1-vkoul@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] arm64: dts: qcom: db845c: Add support for MCP2517FD | expand |
On 19/04/2022 06:33, Vinod Koul wrote: > Add support for onboard MCP2517FD SPI CAN transceiver attached to > SPI0 of RB3. > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > Changes in v2: > - add cs and pinctrl config > - remove misleading comment > > arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 33 ++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts > index 28fe45c5d516..4f4d45be93e3 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts > +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts > @@ -28,6 +28,13 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > > + /* Fixed crystal oscillator dedicated to MCP2517FD */ > + clk40M: can_clock { No underscores in node names. > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <40000000>; > + }; > + > dc12v: dc12v-regulator { > compatible = "regulator-fixed"; > regulator-name = "DC12V"; > @@ -746,6 +753,24 @@ codec { > }; > }; > > +&spi0 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi0_default>; > + cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; > + > + can@0 { > + compatible = "microchip,mcp2517fd"; > + reg = <0>; > + clocks = <&clk40M>; > + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; > + spi-max-frequency = <10000000>; > + vdd-supply = <&vdc_5v>; > + xceiver-supply = <&vdc_5v>; > + status = "okay"; No need for status for new nodes (unless it is an extension of existing node?), it is okay by default. Best regards, Krzysztof
On 19-04-22, 09:37, Krzysztof Kozlowski wrote: > On 19/04/2022 06:33, Vinod Koul wrote: > > Add support for onboard MCP2517FD SPI CAN transceiver attached to > > SPI0 of RB3. > > > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > > --- > > Changes in v2: > > - add cs and pinctrl config > > - remove misleading comment > > > > arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 33 ++++++++++++++++++++++ > > 1 file changed, 33 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts > > index 28fe45c5d516..4f4d45be93e3 100644 > > --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts > > +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts > > @@ -28,6 +28,13 @@ chosen { > > stdout-path = "serial0:115200n8"; > > }; > > > > + /* Fixed crystal oscillator dedicated to MCP2517FD */ > > + clk40M: can_clock { > > No underscores in node names. right, will patch up the original source as well :D > > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <40000000>; > > + }; > > + > > dc12v: dc12v-regulator { > > compatible = "regulator-fixed"; > > regulator-name = "DC12V"; > > @@ -746,6 +753,24 @@ codec { > > }; > > }; > > > > +&spi0 { > > + status = "okay"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&qup_spi0_default>; > > + cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; > > + > > + can@0 { > > + compatible = "microchip,mcp2517fd"; > > + reg = <0>; > > + clocks = <&clk40M>; > > + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; > > + spi-max-frequency = <10000000>; > > + vdd-supply = <&vdc_5v>; > > + xceiver-supply = <&vdc_5v>; > > + status = "okay"; > > No need for status for new nodes (unless it is an extension of existing > node?), it is okay by default. Yep
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 28fe45c5d516..4f4d45be93e3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -28,6 +28,13 @@ chosen { stdout-path = "serial0:115200n8"; }; + /* Fixed crystal oscillator dedicated to MCP2517FD */ + clk40M: can_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + dc12v: dc12v-regulator { compatible = "regulator-fixed"; regulator-name = "DC12V"; @@ -746,6 +753,24 @@ codec { }; }; +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + + can@0 { + compatible = "microchip,mcp2517fd"; + reg = <0>; + clocks = <&clk40M>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdc_5v>; + xceiver-supply = <&vdc_5v>; + status = "okay"; + }; +}; + &spi2 { /* On Low speed expansion */ label = "LS-SPI0"; @@ -1219,3 +1244,11 @@ ov7251_ep: endpoint { }; }; }; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ +&qup_spi0_default { + config { + drive-strength = <6>; + bias-disable; + }; +};
Add support for onboard MCP2517FD SPI CAN transceiver attached to SPI0 of RB3. Signed-off-by: Vinod Koul <vkoul@kernel.org> --- Changes in v2: - add cs and pinctrl config - remove misleading comment arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+)