| Message ID | 20220422120850.769480-7-herve.codina@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | RZN1 USB Host support | expand |
Hi Hervé On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote: > Add the device node for the r9a06g032 internal PCI bridge device. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> Thanks for your patch! > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 { > interrupts = > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > }; > + > + pci_usb: pci@40030000 { > + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; > + device_type = "pci"; > + clocks = <&sysctrl R9A06G032_HCLK_USBH>, > + <&sysctrl R9A06G032_HCLK_USBPM>, > + <&sysctrl R9A06G032_CLK_PCI_USB>; > + clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb"; The clock names need an update, cfr. my comment on the bindings. The rest LGTM, so with the above fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Hervé, On Thu, Apr 28, 2022 at 11:49 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > --- a/arch/arm/boot/dts/r9a06g032.dtsi > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 { > > interrupts = > > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > > }; > > + > > + pci_usb: pci@40030000 { Please preserve sort order (by unit address). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Thu, 28 Apr 2022 11:49:28 +0200 Geert Uytterhoeven <geert@linux-m68k.org> wrote: > Hi Hervé > > On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote: > > Add the device node for the r9a06g032 internal PCI bridge device. > > > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> > > Thanks for your patch! > > > --- a/arch/arm/boot/dts/r9a06g032.dtsi > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 { > > interrupts = > > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > > }; > > + > > + pci_usb: pci@40030000 { > > + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; > > + device_type = "pci"; > > + clocks = <&sysctrl R9A06G032_HCLK_USBH>, > > + <&sysctrl R9A06G032_HCLK_USBPM>, > > + <&sysctrl R9A06G032_CLK_PCI_USB>; > > + clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb"; > > The clock names need an update, cfr. my comment on the bindings. Sure. > > The rest LGTM, so with the above fixed: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Thanks for the review. Regards, Hervé
Hi Geert, On Thu, 28 Apr 2022 11:50:21 +0200 Geert Uytterhoeven <geert@linux-m68k.org> wrote: > Hi Hervé, > > On Thu, Apr 28, 2022 at 11:49 AM Geert Uytterhoeven > <geert@linux-m68k.org> wrote: > > > --- a/arch/arm/boot/dts/r9a06g032.dtsi > > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > > > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 { > > > interrupts = > > > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > > > }; > > > + > > > + pci_usb: pci@40030000 { > > Please preserve sort order (by unit address). Ok, will be done in v4. Thanks, Hervé
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 20286433d3c6..33581f0c55c4 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 { interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; + + pci_usb: pci@40030000 { + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; + device_type = "pci"; + clocks = <&sysctrl R9A06G032_HCLK_USBH>, + <&sysctrl R9A06G032_HCLK_USBPM>, + <&sysctrl R9A06G032_CLK_PCI_USB>; + clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb"; + power-domains = <&sysctrl>; + reg = <0x40030000 0xc00>, + <0x40020000 0x1100>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; + /* Should map all possible DDR as inbound ranges, but + * the IP only supports a 256MB, 512MB, or 1GB window. + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) + */ + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + }; }; timer {
Add the device node for the r9a06g032 internal PCI bridge device. Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)