diff mbox series

[09/11] drm/i915/pvc: Reset support for new copy engines

Message ID 20220502163417.2635462-10-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series i915: Introduce Ponte Vecchio | expand

Commit Message

Matt Roper May 2, 2022, 4:34 p.m. UTC 
This patch adds the reset support for new copy engines
in PVC.

Bspec: 52549
Original-author: CQ Tang
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  8 +++++
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 44 +++++++++++++----------
 2 files changed, 34 insertions(+), 18 deletions(-)

Comments

Souza, Jose May 2, 2022, 6:44 p.m. UTC | #1 
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> This patch adds the reset support for new copy engines
> in PVC.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Bspec: 52549
> Original-author: CQ Tang
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c |  8 +++++
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 44 +++++++++++++----------
>  2 files changed, 34 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 4532c3ea9ace..c6e93db134b1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -390,6 +390,14 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
>  		static const u32 engine_reset_domains[] = {
>  			[RCS0]  = GEN11_GRDOM_RENDER,
>  			[BCS0]  = GEN11_GRDOM_BLT,
> +			[BCS1]  = XEHPC_GRDOM_BLT1,
> +			[BCS2]  = XEHPC_GRDOM_BLT2,
> +			[BCS3]  = XEHPC_GRDOM_BLT3,
> +			[BCS4]  = XEHPC_GRDOM_BLT4,
> +			[BCS5]  = XEHPC_GRDOM_BLT5,
> +			[BCS6]  = XEHPC_GRDOM_BLT6,
> +			[BCS7]  = XEHPC_GRDOM_BLT7,
> +			[BCS8]  = XEHPC_GRDOM_BLT8,
>  			[VCS0]  = GEN11_GRDOM_MEDIA,
>  			[VCS1]  = GEN11_GRDOM_MEDIA2,
>  			[VCS2]  = GEN11_GRDOM_MEDIA3,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index fe09288a3145..98ede9c93f00 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -597,24 +597,32 @@
>  /* GEN11 changed all bit defs except for FULL & RENDER */
>  #define   GEN11_GRDOM_FULL			GEN6_GRDOM_FULL
>  #define   GEN11_GRDOM_RENDER			GEN6_GRDOM_RENDER
> -#define   GEN11_GRDOM_BLT			(1 << 2)
> -#define   GEN11_GRDOM_GUC			(1 << 3)
> -#define   GEN11_GRDOM_MEDIA			(1 << 5)
> -#define   GEN11_GRDOM_MEDIA2			(1 << 6)
> -#define   GEN11_GRDOM_MEDIA3			(1 << 7)
> -#define   GEN11_GRDOM_MEDIA4			(1 << 8)
> -#define   GEN11_GRDOM_MEDIA5			(1 << 9)
> -#define   GEN11_GRDOM_MEDIA6			(1 << 10)
> -#define   GEN11_GRDOM_MEDIA7			(1 << 11)
> -#define   GEN11_GRDOM_MEDIA8			(1 << 12)
> -#define   GEN11_GRDOM_VECS			(1 << 13)
> -#define   GEN11_GRDOM_VECS2			(1 << 14)
> -#define   GEN11_GRDOM_VECS3			(1 << 15)
> -#define   GEN11_GRDOM_VECS4			(1 << 16)
> -#define   GEN11_GRDOM_SFC0			(1 << 17)
> -#define   GEN11_GRDOM_SFC1			(1 << 18)
> -#define   GEN11_GRDOM_SFC2			(1 << 19)
> -#define   GEN11_GRDOM_SFC3			(1 << 20)
> +#define   XEHPC_GRDOM_BLT8			REG_BIT(31)
> +#define   XEHPC_GRDOM_BLT7			REG_BIT(30)
> +#define   XEHPC_GRDOM_BLT6			REG_BIT(29)
> +#define   XEHPC_GRDOM_BLT5			REG_BIT(28)
> +#define   XEHPC_GRDOM_BLT4			REG_BIT(27)
> +#define   XEHPC_GRDOM_BLT3			REG_BIT(26)
> +#define   XEHPC_GRDOM_BLT2			REG_BIT(25)
> +#define   XEHPC_GRDOM_BLT1			REG_BIT(24)
> +#define   GEN11_GRDOM_SFC3			REG_BIT(20)
> +#define   GEN11_GRDOM_SFC2			REG_BIT(19)
> +#define   GEN11_GRDOM_SFC1			REG_BIT(18)
> +#define   GEN11_GRDOM_SFC0			REG_BIT(17)
> +#define   GEN11_GRDOM_VECS4			REG_BIT(16)
> +#define   GEN11_GRDOM_VECS3			REG_BIT(15)
> +#define   GEN11_GRDOM_VECS2			REG_BIT(14)
> +#define   GEN11_GRDOM_VECS			REG_BIT(13)
> +#define   GEN11_GRDOM_MEDIA8			REG_BIT(12)
> +#define   GEN11_GRDOM_MEDIA7			REG_BIT(11)
> +#define   GEN11_GRDOM_MEDIA6			REG_BIT(10)
> +#define   GEN11_GRDOM_MEDIA5			REG_BIT(9)
> +#define   GEN11_GRDOM_MEDIA4			REG_BIT(8)
> +#define   GEN11_GRDOM_MEDIA3			REG_BIT(7)
> +#define   GEN11_GRDOM_MEDIA2			REG_BIT(6)
> +#define   GEN11_GRDOM_MEDIA			REG_BIT(5)
> +#define   GEN11_GRDOM_GUC			REG_BIT(3)
> +#define   GEN11_GRDOM_BLT			REG_BIT(2)
>  #define   GEN11_VCS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << ((instance) >> 1))
>  #define   GEN11_VECS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << (instance))
>
Summers, Stuart May 2, 2022, 10:23 p.m. UTC | #2 
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> This patch adds the reset support for new copy engines
> in PVC.
> 
> Bspec: 52549
> Original-author: CQ Tang
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c |  8 +++++
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 44 +++++++++++++------
> ----
>  2 files changed, 34 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 4532c3ea9ace..c6e93db134b1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -390,6 +390,14 @@ static u32 get_reset_domain(u8 ver, enum
> intel_engine_id id)
>  		static const u32 engine_reset_domains[] = {
>  			[RCS0]  = GEN11_GRDOM_RENDER,
>  			[BCS0]  = GEN11_GRDOM_BLT,
> +			[BCS1]  = XEHPC_GRDOM_BLT1,
> +			[BCS2]  = XEHPC_GRDOM_BLT2,
> +			[BCS3]  = XEHPC_GRDOM_BLT3,
> +			[BCS4]  = XEHPC_GRDOM_BLT4,
> +			[BCS5]  = XEHPC_GRDOM_BLT5,
> +			[BCS6]  = XEHPC_GRDOM_BLT6,
> +			[BCS7]  = XEHPC_GRDOM_BLT7,
> +			[BCS8]  = XEHPC_GRDOM_BLT8,
>  			[VCS0]  = GEN11_GRDOM_MEDIA,
>  			[VCS1]  = GEN11_GRDOM_MEDIA2,
>  			[VCS2]  = GEN11_GRDOM_MEDIA3,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index fe09288a3145..98ede9c93f00 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -597,24 +597,32 @@
>  /* GEN11 changed all bit defs except for FULL & RENDER */
>  #define   GEN11_GRDOM_FULL			GEN6_GRDOM_FULL
>  #define   GEN11_GRDOM_RENDER			GEN6_GRDOM_RENDER
> -#define   GEN11_GRDOM_BLT			(1 << 2)
> -#define   GEN11_GRDOM_GUC			(1 << 3)
> -#define   GEN11_GRDOM_MEDIA			(1 << 5)
> -#define   GEN11_GRDOM_MEDIA2			(1 << 6)
> -#define   GEN11_GRDOM_MEDIA3			(1 << 7)
> -#define   GEN11_GRDOM_MEDIA4			(1 << 8)
> -#define   GEN11_GRDOM_MEDIA5			(1 << 9)
> -#define   GEN11_GRDOM_MEDIA6			(1 << 10)
> -#define   GEN11_GRDOM_MEDIA7			(1 << 11)
> -#define   GEN11_GRDOM_MEDIA8			(1 << 12)
> -#define   GEN11_GRDOM_VECS			(1 << 13)
> -#define   GEN11_GRDOM_VECS2			(1 << 14)
> -#define   GEN11_GRDOM_VECS3			(1 << 15)
> -#define   GEN11_GRDOM_VECS4			(1 << 16)
> -#define   GEN11_GRDOM_SFC0			(1 << 17)
> -#define   GEN11_GRDOM_SFC1			(1 << 18)
> -#define   GEN11_GRDOM_SFC2			(1 << 19)
> -#define   GEN11_GRDOM_SFC3			(1 << 20)
> +#define   XEHPC_GRDOM_BLT8			REG_BIT(31)
> +#define   XEHPC_GRDOM_BLT7			REG_BIT(30)
> +#define   XEHPC_GRDOM_BLT6			REG_BIT(29)
> +#define   XEHPC_GRDOM_BLT5			REG_BIT(28)
> +#define   XEHPC_GRDOM_BLT4			REG_BIT(27)
> +#define   XEHPC_GRDOM_BLT3			REG_BIT(26)
> +#define   XEHPC_GRDOM_BLT2			REG_BIT(25)
> +#define   XEHPC_GRDOM_BLT1			REG_BIT(24)
> +#define   GEN11_GRDOM_SFC3			REG_BIT(20)
> +#define   GEN11_GRDOM_SFC2			REG_BIT(19)
> +#define   GEN11_GRDOM_SFC1			REG_BIT(18)
> +#define   GEN11_GRDOM_SFC0			REG_BIT(17)
> +#define   GEN11_GRDOM_VECS4			REG_BIT(16)
> +#define   GEN11_GRDOM_VECS3			REG_BIT(15)
> +#define   GEN11_GRDOM_VECS2			REG_BIT(14)
> +#define   GEN11_GRDOM_VECS			REG_BIT(13)
> +#define   GEN11_GRDOM_MEDIA8			REG_BIT(12)
> +#define   GEN11_GRDOM_MEDIA7			REG_BIT(11)
> +#define   GEN11_GRDOM_MEDIA6			REG_BIT(10)
> +#define   GEN11_GRDOM_MEDIA5			REG_BIT(9)
> +#define   GEN11_GRDOM_MEDIA4			REG_BIT(8)
> +#define   GEN11_GRDOM_MEDIA3			REG_BIT(7)
> +#define   GEN11_GRDOM_MEDIA2			REG_BIT(6)
> +#define   GEN11_GRDOM_MEDIA			REG_BIT(5)
> +#define   GEN11_GRDOM_GUC			REG_BIT(3)
> +#define   GEN11_GRDOM_BLT			REG_BIT(2)
>  #define   GEN11_VCS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 <<
> ((instance) >> 1))
>  #define   GEN11_VECS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 <<
> (instance))
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 4532c3ea9ace..c6e93db134b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -390,6 +390,14 @@  static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
 		static const u32 engine_reset_domains[] = {
 			[RCS0]  = GEN11_GRDOM_RENDER,
 			[BCS0]  = GEN11_GRDOM_BLT,
+			[BCS1]  = XEHPC_GRDOM_BLT1,
+			[BCS2]  = XEHPC_GRDOM_BLT2,
+			[BCS3]  = XEHPC_GRDOM_BLT3,
+			[BCS4]  = XEHPC_GRDOM_BLT4,
+			[BCS5]  = XEHPC_GRDOM_BLT5,
+			[BCS6]  = XEHPC_GRDOM_BLT6,
+			[BCS7]  = XEHPC_GRDOM_BLT7,
+			[BCS8]  = XEHPC_GRDOM_BLT8,
 			[VCS0]  = GEN11_GRDOM_MEDIA,
 			[VCS1]  = GEN11_GRDOM_MEDIA2,
 			[VCS2]  = GEN11_GRDOM_MEDIA3,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fe09288a3145..98ede9c93f00 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -597,24 +597,32 @@ 
 /* GEN11 changed all bit defs except for FULL & RENDER */
 #define   GEN11_GRDOM_FULL			GEN6_GRDOM_FULL
 #define   GEN11_GRDOM_RENDER			GEN6_GRDOM_RENDER
-#define   GEN11_GRDOM_BLT			(1 << 2)
-#define   GEN11_GRDOM_GUC			(1 << 3)
-#define   GEN11_GRDOM_MEDIA			(1 << 5)
-#define   GEN11_GRDOM_MEDIA2			(1 << 6)
-#define   GEN11_GRDOM_MEDIA3			(1 << 7)
-#define   GEN11_GRDOM_MEDIA4			(1 << 8)
-#define   GEN11_GRDOM_MEDIA5			(1 << 9)
-#define   GEN11_GRDOM_MEDIA6			(1 << 10)
-#define   GEN11_GRDOM_MEDIA7			(1 << 11)
-#define   GEN11_GRDOM_MEDIA8			(1 << 12)
-#define   GEN11_GRDOM_VECS			(1 << 13)
-#define   GEN11_GRDOM_VECS2			(1 << 14)
-#define   GEN11_GRDOM_VECS3			(1 << 15)
-#define   GEN11_GRDOM_VECS4			(1 << 16)
-#define   GEN11_GRDOM_SFC0			(1 << 17)
-#define   GEN11_GRDOM_SFC1			(1 << 18)
-#define   GEN11_GRDOM_SFC2			(1 << 19)
-#define   GEN11_GRDOM_SFC3			(1 << 20)
+#define   XEHPC_GRDOM_BLT8			REG_BIT(31)
+#define   XEHPC_GRDOM_BLT7			REG_BIT(30)
+#define   XEHPC_GRDOM_BLT6			REG_BIT(29)
+#define   XEHPC_GRDOM_BLT5			REG_BIT(28)
+#define   XEHPC_GRDOM_BLT4			REG_BIT(27)
+#define   XEHPC_GRDOM_BLT3			REG_BIT(26)
+#define   XEHPC_GRDOM_BLT2			REG_BIT(25)
+#define   XEHPC_GRDOM_BLT1			REG_BIT(24)
+#define   GEN11_GRDOM_SFC3			REG_BIT(20)
+#define   GEN11_GRDOM_SFC2			REG_BIT(19)
+#define   GEN11_GRDOM_SFC1			REG_BIT(18)
+#define   GEN11_GRDOM_SFC0			REG_BIT(17)
+#define   GEN11_GRDOM_VECS4			REG_BIT(16)
+#define   GEN11_GRDOM_VECS3			REG_BIT(15)
+#define   GEN11_GRDOM_VECS2			REG_BIT(14)
+#define   GEN11_GRDOM_VECS			REG_BIT(13)
+#define   GEN11_GRDOM_MEDIA8			REG_BIT(12)
+#define   GEN11_GRDOM_MEDIA7			REG_BIT(11)
+#define   GEN11_GRDOM_MEDIA6			REG_BIT(10)
+#define   GEN11_GRDOM_MEDIA5			REG_BIT(9)
+#define   GEN11_GRDOM_MEDIA4			REG_BIT(8)
+#define   GEN11_GRDOM_MEDIA3			REG_BIT(7)
+#define   GEN11_GRDOM_MEDIA2			REG_BIT(6)
+#define   GEN11_GRDOM_MEDIA			REG_BIT(5)
+#define   GEN11_GRDOM_GUC			REG_BIT(3)
+#define   GEN11_GRDOM_BLT			REG_BIT(2)
 #define   GEN11_VCS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << ((instance) >> 1))
 #define   GEN11_VECS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << (instance))