| Message ID | 20220331013415.592748-1-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 134b5ce3ed33d3857d5d6e1edcd1656ed9364bbf |
| Headers | show |
| Series | PCI: qcom: Remove ddrss_sf_tbu clock from sc8180x | expand |
On Wed 30 Mar 18:34 PDT 2022, Bjorn Andersson wrote: > The Qualcomm SC8180X platform was piggy backing on the SM8250 > qcom_pcie_cfg, but the platform doesn't have the ddrss_sf_tbu clock, so > it now fails to probe due to the missing clock. > > Give SC8180X its own qcom_pcie_cfg, without the ddrss_sf_tbu flag set. > > Fixes: 0614f98bbb9f ("PCI: qcom: Add ddrss_sf_tbu flag") > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Ping. Would be nice to have this regression fix picked up for v5.18... Thanks, Bjorn > --- > drivers/pci/controller/dwc/pcie-qcom.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 6ab90891801d..816028c0f6ed 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1550,6 +1550,11 @@ static const struct qcom_pcie_cfg sc7280_cfg = { > .pipe_clk_need_muxing = true, > }; > > +static const struct qcom_pcie_cfg sc8180x_cfg = { > + .ops = &ops_1_9_0, > + .has_tbu_clk = true, > +}; > + > static const struct dw_pcie_ops dw_pcie_ops = { > .link_up = qcom_pcie_link_up, > .start_link = qcom_pcie_start_link, > @@ -1656,7 +1661,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, > { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, > { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, > - { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, > + { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg }, > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, > { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, > -- > 2.35.1 >
On Thu, 31 Mar 2022 at 04:31, Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > The Qualcomm SC8180X platform was piggy backing on the SM8250 > qcom_pcie_cfg, but the platform doesn't have the ddrss_sf_tbu clock, so > it now fails to probe due to the missing clock. > > Give SC8180X its own qcom_pcie_cfg, without the ddrss_sf_tbu flag set. > > Fixes: 0614f98bbb9f ("PCI: qcom: Add ddrss_sf_tbu flag") > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 6ab90891801d..816028c0f6ed 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1550,6 +1550,11 @@ static const struct qcom_pcie_cfg sc7280_cfg = { > .pipe_clk_need_muxing = true, > }; > > +static const struct qcom_pcie_cfg sc8180x_cfg = { > + .ops = &ops_1_9_0, > + .has_tbu_clk = true, > +}; > + > static const struct dw_pcie_ops dw_pcie_ops = { > .link_up = qcom_pcie_link_up, > .start_link = qcom_pcie_start_link, > @@ -1656,7 +1661,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, > { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, > { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, > - { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, > + { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg }, > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, > { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, > -- > 2.35.1 >
On 3/31/22 04:34, Bjorn Andersson wrote: > The Qualcomm SC8180X platform was piggy backing on the SM8250 > qcom_pcie_cfg, but the platform doesn't have the ddrss_sf_tbu clock, so > it now fails to probe due to the missing clock. > > Give SC8180X its own qcom_pcie_cfg, without the ddrss_sf_tbu flag set. > > Fixes: 0614f98bbb9f ("PCI: qcom: Add ddrss_sf_tbu flag") > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
On 3/30/22 8:34 PM, Bjorn Andersson wrote: > The Qualcomm SC8180X platform was piggy backing on the SM8250 > qcom_pcie_cfg, but the platform doesn't have the ddrss_sf_tbu clock, so > it now fails to probe due to the missing clock. > > Give SC8180X its own qcom_pcie_cfg, without the ddrss_sf_tbu flag set. > > Fixes: 0614f98bbb9f ("PCI: qcom: Add ddrss_sf_tbu flag") > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 6ab90891801d..816028c0f6ed 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1550,6 +1550,11 @@ static const struct qcom_pcie_cfg sc7280_cfg = { > .pipe_clk_need_muxing = true, > }; > > +static const struct qcom_pcie_cfg sc8180x_cfg = { > + .ops = &ops_1_9_0, > + .has_tbu_clk = true, > +}; > + > static const struct dw_pcie_ops dw_pcie_ops = { > .link_up = qcom_pcie_link_up, > .start_link = qcom_pcie_start_link, > @@ -1656,7 +1661,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, > { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, > { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, > - { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, > + { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg }, > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, > { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, Hi Bjorn, Tested on the Lenovo Flex 5G and fixes the issue I saw. Tested-by: Steev Klimaszewski <steev@kali.org>
On Wed, Mar 30, 2022 at 06:34:15PM -0700, Bjorn Andersson wrote: > The Qualcomm SC8180X platform was piggy backing on the SM8250 > qcom_pcie_cfg, but the platform doesn't have the ddrss_sf_tbu clock, so > it now fails to probe due to the missing clock. > > Give SC8180X its own qcom_pcie_cfg, without the ddrss_sf_tbu flag set. > > Fixes: 0614f98bbb9f ("PCI: qcom: Add ddrss_sf_tbu flag") > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Since this fixes a regression that we added in v5.18-rc1, I applied this to for-linus for v5.18. Thanks! > --- > drivers/pci/controller/dwc/pcie-qcom.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 6ab90891801d..816028c0f6ed 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1550,6 +1550,11 @@ static const struct qcom_pcie_cfg sc7280_cfg = { > .pipe_clk_need_muxing = true, > }; > > +static const struct qcom_pcie_cfg sc8180x_cfg = { > + .ops = &ops_1_9_0, > + .has_tbu_clk = true, > +}; > + > static const struct dw_pcie_ops dw_pcie_ops = { > .link_up = qcom_pcie_link_up, > .start_link = qcom_pcie_start_link, > @@ -1656,7 +1661,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, > { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, > { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, > - { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, > + { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg }, > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, > { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, > -- > 2.35.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 6ab90891801d..816028c0f6ed 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1550,6 +1550,11 @@ static const struct qcom_pcie_cfg sc7280_cfg = { .pipe_clk_need_muxing = true, }; +static const struct qcom_pcie_cfg sc8180x_cfg = { + .ops = &ops_1_9_0, + .has_tbu_clk = true, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, @@ -1656,7 +1661,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, - { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, + { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
The Qualcomm SC8180X platform was piggy backing on the SM8250 qcom_pcie_cfg, but the platform doesn't have the ddrss_sf_tbu clock, so it now fails to probe due to the missing clock. Give SC8180X its own qcom_pcie_cfg, without the ddrss_sf_tbu flag set. Fixes: 0614f98bbb9f ("PCI: qcom: Add ddrss_sf_tbu flag") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)