| Message ID | 20220428133753.8348-2-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add mt8186 dsi compatoble & Convert dsi_dtbinding to .yaml | expand |
On Thu, 28 Apr 2022 21:37:50 +0800, Rex-BC Chen wrote: > From: Xinlei Lee <xinlei.lee@mediatek.com> > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > --- > .../display/mediatek/mediatek,dsi.txt | 62 --------- > .../display/mediatek/mediatek,dsi.yaml | 122 ++++++++++++++++++ > 2 files changed, 122 insertions(+), 62 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/ dsi@1400c000: compatible: ['mediatek,mt7623-dsi', 'mediatek,mt2701-dsi'] is too long arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dtb arch/arm/boot/dts/mt7623n-rfb-emmc.dtb dsi@14014000: #address-cells:0:0: 2 was expected arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb dsi@14014000: 'port' is a required property arch/arm64/boot/dts/mediatek/mt8183-evb.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb dsi@14014000: #size-cells:0:0: 2 was expected arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb dsi@1401b000: 'port' is a required property arch/arm64/boot/dts/mediatek/mt8173-elm.dtb arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtb arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dtb
On Thu, 2022-04-28 at 15:33 -0500, Rob Herring wrote: > On Thu, 28 Apr 2022 21:37:50 +0800, Rex-BC Chen wrote: > > From: Xinlei Lee <xinlei.lee@mediatek.com> > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > --- > > .../display/mediatek/mediatek,dsi.txt | 62 --------- > > .../display/mediatek/mediatek,dsi.yaml | 122 > > ++++++++++++++++++ > > 2 files changed, 122 insertions(+), 62 deletions(-) > > delete mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > > l > > > > Running 'make dtbs_check' with the schema in this patch gives the > following warnings. Consider if they are expected or the schema is > incorrect. These may not be new warnings. > > Note that it is not yet a requirement to have 0 warnings for > dtbs_check. > This will change in the future. > > Full log is available here: > https://urldefense.com/v3/__https://patchwork.ozlabs.org/patch/__;!!CTRNKA9wMg0ARbw!wKbRsUmeUS_4mtOwj1t30buVNEilHYYhsUmEd5MvZ7P9VyDXg6cikERof47mkwETQzFL$ > > > > dsi@1400c000: compatible: ['mediatek,mt7623-dsi', 'mediatek,mt2701- > dsi'] is too long > arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dtb > arch/arm/boot/dts/mt7623n-rfb-emmc.dtb > > dsi@14014000: #address-cells:0:0: 2 was expected > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14- > sku2.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > sku1.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > sku6.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > sku7.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper- > sku16.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > sku0.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > sku1.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb > > dsi@14014000: 'port' is a required property > arch/arm64/boot/dts/mediatek/mt8183-evb.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14- > sku2.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > sku1.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > sku6.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > sku7.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper- > sku16.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > sku0.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > sku1.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb > > dsi@14014000: #size-cells:0:0: 2 was expected > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14- > sku2.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > sku1.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > sku6.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > sku7.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper- > sku16.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > sku0.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > sku1.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb > > dsi@1401b000: 'port' is a required property > arch/arm64/boot/dts/mediatek/mt8173-elm.dtb > arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtb > arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dtb > Hello Rob, Thanks for your comments. The purpose of this series is not to fix dts for previous SoCs. Therefore, if there is a chance, we could send another series to fix them. Thanks. BRs, Rex
On Fri, Apr 29, 2022 at 09:55:37AM +0800, Rex-BC Chen wrote: > On Thu, 2022-04-28 at 15:33 -0500, Rob Herring wrote: > > On Thu, 28 Apr 2022 21:37:50 +0800, Rex-BC Chen wrote: > > > From: Xinlei Lee <xinlei.lee@mediatek.com> > > > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > > --- > > > .../display/mediatek/mediatek,dsi.txt | 62 --------- > > > .../display/mediatek/mediatek,dsi.yaml | 122 > > > ++++++++++++++++++ > > > 2 files changed, 122 insertions(+), 62 deletions(-) > > > delete mode 100644 > > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > > create mode 100644 > > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > > > l > > > > > > > Running 'make dtbs_check' with the schema in this patch gives the > > following warnings. Consider if they are expected or the schema is > > incorrect. These may not be new warnings. > > > > Note that it is not yet a requirement to have 0 warnings for > > dtbs_check. > > This will change in the future. > > > > Full log is available here: > > https://urldefense.com/v3/__https://patchwork.ozlabs.org/patch/__;!!CTRNKA9wMg0ARbw!wKbRsUmeUS_4mtOwj1t30buVNEilHYYhsUmEd5MvZ7P9VyDXg6cikERof47mkwETQzFL$ > > > > > > > > dsi@1400c000: compatible: ['mediatek,mt7623-dsi', 'mediatek,mt2701- > > dsi'] is too long > > arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dtb > > arch/arm/boot/dts/mt7623n-rfb-emmc.dtb > > > > dsi@14014000: #address-cells:0:0: 2 was expected > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14- > > sku2.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > sku1.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > sku6.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > sku7.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper- > > sku16.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > sku0.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > sku1.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb > > > > dsi@14014000: 'port' is a required property > > arch/arm64/boot/dts/mediatek/mt8183-evb.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14- > > sku2.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > sku1.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > sku6.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > sku7.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper- > > sku16.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > sku0.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > sku1.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb > > > > dsi@14014000: #size-cells:0:0: 2 was expected > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14- > > sku2.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > sku1.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > sku6.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > sku7.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper- > > sku16.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > sku0.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > sku1.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb > > > > dsi@1401b000: 'port' is a required property > > arch/arm64/boot/dts/mediatek/mt8173-elm.dtb > > arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtb > > arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dtb > > > > Hello Rob, > > Thanks for your comments. > The purpose of this series is not to fix dts for previous SoCs. > Therefore, if there is a chance, we could send another series to fix > them. Conversions often find that the actual dts files vary a bit more than the binding doc said. You should look at the warnings and decide if they should be fixed or the schema relaxed. It's a judgement call. I have no idea if you did that already or not, so I send this out on conversions. The check runs automatically, but sending it I review briefly. Rob
On Fri, 2022-04-29 at 15:06 -0500, Rob Herring wrote: > On Fri, Apr 29, 2022 at 09:55:37AM +0800, Rex-BC Chen wrote: > > On Thu, 2022-04-28 at 15:33 -0500, Rob Herring wrote: > > > On Thu, 28 Apr 2022 21:37:50 +0800, Rex-BC Chen wrote: > > > > From: Xinlei Lee <xinlei.lee@mediatek.com> > > > > > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > > > > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > > > --- > > > > .../display/mediatek/mediatek,dsi.txt | 62 --------- > > > > .../display/mediatek/mediatek,dsi.yaml | 122 > > > > ++++++++++++++++++ > > > > 2 files changed, 122 insertions(+), 62 deletions(-) > > > > delete mode 100644 > > > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi > > > > .txt > > > > create mode 100644 > > > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi > > > > .yam > > > > l > > > > > > > > > > Running 'make dtbs_check' with the schema in this patch gives the > > > following warnings. Consider if they are expected or the schema > > > is > > > incorrect. These may not be new warnings. > > > > > > Note that it is not yet a requirement to have 0 warnings for > > > dtbs_check. > > > This will change in the future. > > > > > > Full log is available here: > > > https://urldefense.com/v3/__https://patchwork.ozlabs.org/patch/__;!!CTRNKA9wMg0ARbw!wKbRsUmeUS_4mtOwj1t30buVNEilHYYhsUmEd5MvZ7P9VyDXg6cikERof47mkwETQzFL$ > > > > > > > > > > > > dsi@1400c000: compatible: ['mediatek,mt7623-dsi', > > > 'mediatek,mt2701- > > > dsi'] is too long > > > arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dtb > > > arch/arm/boot/dts/mt7623n-rfb-emmc.dtb > > > > > > dsi@14014000: #address-cells:0:0: 2 was expected > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14- > > > sku2.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > > sku1.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > > sku6.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > > sku7.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper- > > > sku16.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > > sku0.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > > sku1.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb > > > > > > dsi@14014000: 'port' is a required property > > > arch/arm64/boot/dts/mediatek/mt8183-evb.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14- > > > sku2.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > > sku1.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > > sku6.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > > sku7.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper- > > > sku16.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > > sku0.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > > sku1.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb > > > > > > dsi@14014000: #size-cells:0:0: 2 was expected > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14- > > > sku2.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > > sku1.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > > sku6.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel- > > > sku7.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper- > > > sku16.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > > sku0.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow- > > > sku1.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb > > > arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb > > > > > > dsi@1401b000: 'port' is a required property > > > arch/arm64/boot/dts/mediatek/mt8173-elm.dtb > > > arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtb > > > arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dtb > > > > > > > Hello Rob, > > > > Thanks for your comments. > > The purpose of this series is not to fix dts for previous SoCs. > > Therefore, if there is a chance, we could send another series to > > fix > > them. > > Conversions often find that the actual dts files vary a bit more > than > the binding doc said. You should look at the warnings and decide if > they > should be fixed or the schema relaxed. It's a judgement call. I have > no > idea if you did that already or not, so I send this out on > conversions. > The check runs automatically, but sending it I review briefly. > > Rob Hello Rob, Thanks for your explanation! In addition, do you have any suggestion for this conversion? BRs, Rex
On Thu, Apr 28, 2022 at 09:37:50PM +0800, Rex-BC Chen wrote: > From: Xinlei Lee <xinlei.lee@mediatek.com> > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > --- > .../display/mediatek/mediatek,dsi.txt | 62 --------- > .../display/mediatek/mediatek,dsi.yaml | 122 ++++++++++++++++++ > 2 files changed, 122 insertions(+), 62 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > deleted file mode 100644 > index 36b01458f45c..000000000000 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ /dev/null > @@ -1,62 +0,0 @@ > -Mediatek DSI Device > -=================== > - > -The Mediatek DSI function block is a sink of the display subsystem and can > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- > -channel output. > - > -Required properties: > -- compatible: "mediatek,<chip>-dsi" > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. > -- reg: Physical base address and length of the controller's registers > -- interrupts: The interrupt signal from the function block. > -- clocks: device clocks > - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. > -- clock-names: must contain "engine", "digital", and "hs" > -- phys: phandle link to the MIPI D-PHY controller. > -- phy-names: must contain "dphy" > -- port: Output port node with endpoint definitions as described in > - Documentation/devicetree/bindings/graph.txt. This port should be connected > - to the input port of an attached DSI panel or DSI-to-eDP encoder chip. > - > -Optional properties: > -- resets: list of phandle + reset specifier pair, as described in [1]. > - > -[1] Documentation/devicetree/bindings/reset/reset.txt > - > -MIPI TX Configuration Module > -============================ > - > -See phy/mediatek,dsi-phy.yaml > - > -Example: > - > -mipi_tx0: mipi-dphy@10215000 { > - compatible = "mediatek,mt8173-mipi-tx"; > - reg = <0 0x10215000 0 0x1000>; > - clocks = <&clk26m>; > - clock-output-names = "mipi_tx0_pll"; > - #clock-cells = <0>; > - #phy-cells = <0>; > - drive-strength-microamp = <4600>; > - nvmem-cells= <&mipi_tx_calibration>; > - nvmem-cell-names = "calibration-data"; > -}; > - > -dsi0: dsi@1401b000 { > - compatible = "mediatek,mt8173-dsi"; > - reg = <0 0x1401b000 0 0x1000>; > - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > - <&mipi_tx0>; > - clock-names = "engine", "digital", "hs"; > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > - phys = <&mipi_tx0>; > - phy-names = "dphy"; > - > - port { > - dsi0_out: endpoint { > - remote-endpoint = <&panel_in>; > - }; > - }; > -}; > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > new file mode 100644 > index 000000000000..2ca9229ef69e > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > @@ -0,0 +1,122 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek DSI Controller Device Tree Bindings > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > + - Philipp Zabel <p.zabel@pengutronix.de> > + - Jitao Shi <jitao.shi@mediatek.com> > + - Xinlei Lee <xinlei.lee@mediatek.com> > + > +description: | > + The MediaTek DSI function block is a sink of the display subsystem and can > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- > + channel output. > + > +allOf: > + - $ref: /schemas/display/dsi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-dsi > + - mediatek,mt7623-dsi > + - mediatek,mt8167-dsi > + - mediatek,mt8173-dsi > + - mediatek,mt8183-dsi > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Engine Clock > + - description: Digital Clock > + - description: HS Clock > + > + clock-names: > + items: > + - const: engine > + - const: digital > + - const: hs > + > + resets: > + maxItems: 1 > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - const: dphy > + > + port: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output port node. This port should be connected to the input > + port of an attached DSI panel or DSI-to-eDP encoder chip. > + > + 1 blank line > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 Did you try adding these? Because they are wrong and will contradict dsi-controller.yaml. Rob
On Tue, 2022-05-03 at 13:01 -0500, Rob Herring wrote: > On Thu, Apr 28, 2022 at 09:37:50PM +0800, Rex-BC Chen wrote: > > From: Xinlei Lee <xinlei.lee@mediatek.com> > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > --- > > .../display/mediatek/mediatek,dsi.txt | 62 --------- > > .../display/mediatek/mediatek,dsi.yaml | 122 > > ++++++++++++++++++ > > 2 files changed, 122 insertions(+), 62 deletions(-) > > delete mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > > l > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > deleted file mode 100644 > > index 36b01458f45c..000000000000 > > --- > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > +++ /dev/null > > @@ -1,62 +0,0 @@ > > -Mediatek DSI Device > > -=================== > > - > > -The Mediatek DSI function block is a sink of the display subsystem > > and can > > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > -channel output. > > - > > -Required properties: > > -- compatible: "mediatek,<chip>-dsi" > > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and > > mt8183. > > -- reg: Physical base address and length of the controller's > > registers > > -- interrupts: The interrupt signal from the function block. > > -- clocks: device clocks > > - See Documentation/devicetree/bindings/clock/clock-bindings.txt > > for details. > > -- clock-names: must contain "engine", "digital", and "hs" > > -- phys: phandle link to the MIPI D-PHY controller. > > -- phy-names: must contain "dphy" > > -- port: Output port node with endpoint definitions as described in > > - Documentation/devicetree/bindings/graph.txt. This port should be > > connected > > - to the input port of an attached DSI panel or DSI-to-eDP encoder > > chip. > > - > > -Optional properties: > > -- resets: list of phandle + reset specifier pair, as described in > > [1]. > > - > > -[1] Documentation/devicetree/bindings/reset/reset.txt > > - > > -MIPI TX Configuration Module > > -============================ > > - > > -See phy/mediatek,dsi-phy.yaml > > - > > -Example: > > - > > -mipi_tx0: mipi-dphy@10215000 { > > - compatible = "mediatek,mt8173-mipi-tx"; > > - reg = <0 0x10215000 0 0x1000>; > > - clocks = <&clk26m>; > > - clock-output-names = "mipi_tx0_pll"; > > - #clock-cells = <0>; > > - #phy-cells = <0>; > > - drive-strength-microamp = <4600>; > > - nvmem-cells= <&mipi_tx_calibration>; > > - nvmem-cell-names = "calibration-data"; > > -}; > > - > > -dsi0: dsi@1401b000 { > > - compatible = "mediatek,mt8173-dsi"; > > - reg = <0 0x1401b000 0 0x1000>; > > - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; > > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > > - <&mipi_tx0>; > > - clock-names = "engine", "digital", "hs"; > > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > > - phys = <&mipi_tx0>; > > - phy-names = "dphy"; > > - > > - port { > > - dsi0_out: endpoint { > > - remote-endpoint = <&panel_in>; > > - }; > > - }; > > -}; > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > new file mode 100644 > > index 000000000000..2ca9229ef69e > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > @@ -0,0 +1,122 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vunKIJlM$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vns85I56$ > > > > + > > +title: MediaTek DSI Controller Device Tree Bindings > > + > > +maintainers: > > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > > + - Philipp Zabel <p.zabel@pengutronix.de> > > + - Jitao Shi <jitao.shi@mediatek.com> > > + - Xinlei Lee <xinlei.lee@mediatek.com> > > + > > +description: | > > + The MediaTek DSI function block is a sink of the display > > subsystem and can > > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > + channel output. > > + > > +allOf: > > + - $ref: /schemas/display/dsi-controller.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt2701-dsi > > + - mediatek,mt7623-dsi > > + - mediatek,mt8167-dsi > > + - mediatek,mt8173-dsi > > + - mediatek,mt8183-dsi > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Engine Clock > > + - description: Digital Clock > > + - description: HS Clock > > + > > + clock-names: > > + items: > > + - const: engine > > + - const: digital > > + - const: hs > > + > > + resets: > > + maxItems: 1 > > + > > + phys: > > + maxItems: 1 > > + > > + phy-names: > > + items: > > + - const: dphy > > + > > + port: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Output port node. This port should be connected to the input > > + port of an attached DSI panel or DSI-to-eDP encoder chip. > > + > > + > > 1 blank line Hello Rob, Thanks for your review. ok. I will do this in next version. > > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > Did you try adding these? Because they are wrong and will contradict > dsi-controller.yaml. > We have some mistake. There will not be any sub node for mediatek dsi, so I will drop this modification in next version. BRs, Rex > Rob
On Tue, 2022-05-03 at 13:01 -0500, Rob Herring wrote: > On Thu, Apr 28, 2022 at 09:37:50PM +0800, Rex-BC Chen wrote: > > From: Xinlei Lee <xinlei.lee@mediatek.com> > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > --- > > .../display/mediatek/mediatek,dsi.txt | 62 --------- > > .../display/mediatek/mediatek,dsi.yaml | 122 > > ++++++++++++++++++ > > 2 files changed, 122 insertions(+), 62 deletions(-) > > delete mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > > l > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > deleted file mode 100644 > > index 36b01458f45c..000000000000 > > --- > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > +++ /dev/null > > @@ -1,62 +0,0 @@ > > -Mediatek DSI Device > > -=================== > > - > > -The Mediatek DSI function block is a sink of the display subsystem > > and can > > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > -channel output. > > - > > -Required properties: > > -- compatible: "mediatek,<chip>-dsi" > > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and > > mt8183. > > -- reg: Physical base address and length of the controller's > > registers > > -- interrupts: The interrupt signal from the function block. > > -- clocks: device clocks > > - See Documentation/devicetree/bindings/clock/clock-bindings.txt > > for details. > > -- clock-names: must contain "engine", "digital", and "hs" > > -- phys: phandle link to the MIPI D-PHY controller. > > -- phy-names: must contain "dphy" > > -- port: Output port node with endpoint definitions as described in > > - Documentation/devicetree/bindings/graph.txt. This port should be > > connected > > - to the input port of an attached DSI panel or DSI-to-eDP encoder > > chip. > > - > > -Optional properties: > > -- resets: list of phandle + reset specifier pair, as described in > > [1]. > > - > > -[1] Documentation/devicetree/bindings/reset/reset.txt > > - > > -MIPI TX Configuration Module > > -============================ > > - > > -See phy/mediatek,dsi-phy.yaml > > - > > -Example: > > - > > -mipi_tx0: mipi-dphy@10215000 { > > - compatible = "mediatek,mt8173-mipi-tx"; > > - reg = <0 0x10215000 0 0x1000>; > > - clocks = <&clk26m>; > > - clock-output-names = "mipi_tx0_pll"; > > - #clock-cells = <0>; > > - #phy-cells = <0>; > > - drive-strength-microamp = <4600>; > > - nvmem-cells= <&mipi_tx_calibration>; > > - nvmem-cell-names = "calibration-data"; > > -}; > > - > > -dsi0: dsi@1401b000 { > > - compatible = "mediatek,mt8173-dsi"; > > - reg = <0 0x1401b000 0 0x1000>; > > - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; > > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > > - <&mipi_tx0>; > > - clock-names = "engine", "digital", "hs"; > > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > > - phys = <&mipi_tx0>; > > - phy-names = "dphy"; > > - > > - port { > > - dsi0_out: endpoint { > > - remote-endpoint = <&panel_in>; > > - }; > > - }; > > -}; > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > new file mode 100644 > > index 000000000000..2ca9229ef69e > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > @@ -0,0 +1,122 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vunKIJlM$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vns85I56$ > > > > + > > +title: MediaTek DSI Controller Device Tree Bindings > > + > > +maintainers: > > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > > + - Philipp Zabel <p.zabel@pengutronix.de> > > + - Jitao Shi <jitao.shi@mediatek.com> > > + - Xinlei Lee <xinlei.lee@mediatek.com> > > + > > +description: | > > + The MediaTek DSI function block is a sink of the display > > subsystem and can > > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > + channel output. > > + > > +allOf: > > + - $ref: /schemas/display/dsi-controller.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt2701-dsi > > + - mediatek,mt7623-dsi > > + - mediatek,mt8167-dsi > > + - mediatek,mt8173-dsi > > + - mediatek,mt8183-dsi > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Engine Clock > > + - description: Digital Clock > > + - description: HS Clock > > + > > + clock-names: > > + items: > > + - const: engine > > + - const: digital > > + - const: hs > > + > > + resets: > > + maxItems: 1 > > + > > + phys: > > + maxItems: 1 > > + > > + phy-names: > > + items: > > + - const: dphy > > + > > + port: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Output port node. This port should be connected to the input > > + port of an attached DSI panel or DSI-to-eDP encoder chip. > > + > > + > > 1 blank line > > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > Did you try adding these? Because they are wrong and will contradict > dsi-controller.yaml. > Hello Rob, Sorry, I response something wrong in previous letter. We could have sub nodes in mediatek dsi. But we do not need to define this: "#address-cells": const: 2 "#size-cells": const: 2 I will drop them. Thanks! BRs, Rex > Rob
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt deleted file mode 100644 index 36b01458f45c..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ /dev/null @@ -1,62 +0,0 @@ -Mediatek DSI Device -=================== - -The Mediatek DSI function block is a sink of the display subsystem and can -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- -channel output. - -Required properties: -- compatible: "mediatek,<chip>-dsi" -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "engine", "digital", and "hs" -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy" -- port: Output port node with endpoint definitions as described in - Documentation/devicetree/bindings/graph.txt. This port should be connected - to the input port of an attached DSI panel or DSI-to-eDP encoder chip. - -Optional properties: -- resets: list of phandle + reset specifier pair, as described in [1]. - -[1] Documentation/devicetree/bindings/reset/reset.txt - -MIPI TX Configuration Module -============================ - -See phy/mediatek,dsi-phy.yaml - -Example: - -mipi_tx0: mipi-dphy@10215000 { - compatible = "mediatek,mt8173-mipi-tx"; - reg = <0 0x10215000 0 0x1000>; - clocks = <&clk26m>; - clock-output-names = "mipi_tx0_pll"; - #clock-cells = <0>; - #phy-cells = <0>; - drive-strength-microamp = <4600>; - nvmem-cells= <&mipi_tx_calibration>; - nvmem-cell-names = "calibration-data"; -}; - -dsi0: dsi@1401b000 { - compatible = "mediatek,mt8173-dsi"; - reg = <0 0x1401b000 0 0x1000>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, - <&mipi_tx0>; - clock-names = "engine", "digital", "hs"; - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; - phys = <&mipi_tx0>; - phy-names = "dphy"; - - port { - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml new file mode 100644 index 000000000000..2ca9229ef69e --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DSI Controller Device Tree Bindings + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Philipp Zabel <p.zabel@pengutronix.de> + - Jitao Shi <jitao.shi@mediatek.com> + - Xinlei Lee <xinlei.lee@mediatek.com> + +description: | + The MediaTek DSI function block is a sink of the display subsystem and can + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- + channel output. + +allOf: + - $ref: /schemas/display/dsi-controller.yaml# + +properties: + compatible: + enum: + - mediatek,mt2701-dsi + - mediatek,mt7623-dsi + - mediatek,mt8167-dsi + - mediatek,mt8173-dsi + - mediatek,mt8183-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Engine Clock + - description: Digital Clock + - description: HS Clock + + clock-names: + items: + - const: engine + - const: digital + - const: hs + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + items: + - const: dphy + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port node. This port should be connected to the input + port of an attached DSI panel or DSI-to-eDP encoder chip. + + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + - clock-names + - phys + - phy-names + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt8183-power.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/reset/mt8183-resets.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DSI0_MM>, + <&mmsys CLK_MM_DSI0_IF>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + port { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + +...