| Message ID | 20220504190756.466270-4-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/12] drm/i915: Drop IPC from display 13 and newer | expand |
On Wed, May 04, 2022 at 12:07:48PM -0700, José Roberto de Souza wrote: > No need to have this parameter in intel_device_info struct > as all platforms with graphics version 6 or newer have software > support for this feature. > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 3 ++- > drivers/gpu/drm/i915/i915_pci.c | 8 -------- > drivers/gpu/drm/i915/intel_device_info.h | 1 - > 3 files changed, 2 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 3a3d57485b09c..d29dca83185ac 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1308,7 +1308,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) > #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0) > > -#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) > +/* ilk does support rc6, but we do not implement [power] contexts */ > +#define HAS_RC6(dev_priv) (GRAPHICS_VER(dev_priv) >= 6) > #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) > #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index df20818ce8eae..90584c462f225 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -376,8 +376,6 @@ static const struct intel_device_info gm45_info = { > .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ > .has_snoop = true, \ > .has_coherent_ggtt = true, \ > - /* ilk does support rc6, but we do not implement [power] contexts */ \ > - .has_rc6 = 0, \ > .dma_mask_size = 36, \ > I9XX_PIPE_OFFSETS, \ > I9XX_CURSOR_OFFSETS, \ > @@ -407,7 +405,6 @@ static const struct intel_device_info ilk_m_info = { > .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ > .has_coherent_ggtt = true, \ > .has_llc = 1, \ > - .has_rc6 = 1, \ > .has_rc6p = 1, \ > .has_rps = true, \ > .dma_mask_size = 40, \ > @@ -458,7 +455,6 @@ static const struct intel_device_info snb_m_gt2_info = { > .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ > .has_coherent_ggtt = true, \ > .has_llc = 1, \ > - .has_rc6 = 1, \ > .has_rc6p = 1, \ > .has_reset_engine = true, \ > .has_rps = true, \ > @@ -518,7 +514,6 @@ static const struct intel_device_info vlv_info = { > .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), > .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), > .has_runtime_pm = 1, > - .has_rc6 = 1, > .has_reset_engine = true, > .has_rps = true, > .display.has_gmch = 1, > @@ -617,7 +612,6 @@ static const struct intel_device_info chv_info = { > .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), > .has_64bit_reloc = 1, > .has_runtime_pm = 1, > - .has_rc6 = 1, > .has_rps = true, > .has_logical_ring_contexts = 1, > .display.has_gmch = 1, > @@ -699,7 +693,6 @@ static const struct intel_device_info skl_gt4_info = { > .display.has_psr_hw_tracking = 1, \ > .has_runtime_pm = 1, \ > .display.has_dmc = 1, \ > - .has_rc6 = 1, \ > .has_rps = true, \ > .display.has_dp_mst = 1, \ > .has_logical_ring_contexts = 1, \ > @@ -1005,7 +998,6 @@ static const struct intel_device_info adl_p_info = { > .has_logical_ring_contexts = 1, \ > .has_logical_ring_elsq = 1, \ > .has_mslices = 1, \ > - .has_rc6 = 1, \ > .has_reset_engine = 1, \ > .has_rps = 1, \ > .has_runtime_pm = 1, \ > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 6d2eafaab4ef0..b3244170c4638 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -156,7 +156,6 @@ enum intel_ppgtt_type { > func(has_mslices); \ > func(has_pooled_eu); \ > func(has_pxp); \ > - func(has_rc6); \ > func(has_rc6p); \ > func(has_rps); \ > func(has_runtime_pm); \ > -- > 2.36.0 >
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3a3d57485b09c..d29dca83185ac 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1308,7 +1308,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0) -#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) +/* ilk does support rc6, but we do not implement [power] contexts */ +#define HAS_RC6(dev_priv) (GRAPHICS_VER(dev_priv) >= 6) #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index df20818ce8eae..90584c462f225 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -376,8 +376,6 @@ static const struct intel_device_info gm45_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ .has_snoop = true, \ .has_coherent_ggtt = true, \ - /* ilk does support rc6, but we do not implement [power] contexts */ \ - .has_rc6 = 0, \ .dma_mask_size = 36, \ I9XX_PIPE_OFFSETS, \ I9XX_CURSOR_OFFSETS, \ @@ -407,7 +405,6 @@ static const struct intel_device_info ilk_m_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ .has_coherent_ggtt = true, \ .has_llc = 1, \ - .has_rc6 = 1, \ .has_rc6p = 1, \ .has_rps = true, \ .dma_mask_size = 40, \ @@ -458,7 +455,6 @@ static const struct intel_device_info snb_m_gt2_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ .has_coherent_ggtt = true, \ .has_llc = 1, \ - .has_rc6 = 1, \ .has_rc6p = 1, \ .has_reset_engine = true, \ .has_rps = true, \ @@ -518,7 +514,6 @@ static const struct intel_device_info vlv_info = { .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), .has_runtime_pm = 1, - .has_rc6 = 1, .has_reset_engine = true, .has_rps = true, .display.has_gmch = 1, @@ -617,7 +612,6 @@ static const struct intel_device_info chv_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), .has_64bit_reloc = 1, .has_runtime_pm = 1, - .has_rc6 = 1, .has_rps = true, .has_logical_ring_contexts = 1, .display.has_gmch = 1, @@ -699,7 +693,6 @@ static const struct intel_device_info skl_gt4_info = { .display.has_psr_hw_tracking = 1, \ .has_runtime_pm = 1, \ .display.has_dmc = 1, \ - .has_rc6 = 1, \ .has_rps = true, \ .display.has_dp_mst = 1, \ .has_logical_ring_contexts = 1, \ @@ -1005,7 +998,6 @@ static const struct intel_device_info adl_p_info = { .has_logical_ring_contexts = 1, \ .has_logical_ring_elsq = 1, \ .has_mslices = 1, \ - .has_rc6 = 1, \ .has_reset_engine = 1, \ .has_rps = 1, \ .has_runtime_pm = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 6d2eafaab4ef0..b3244170c4638 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -156,7 +156,6 @@ enum intel_ppgtt_type { func(has_mslices); \ func(has_pooled_eu); \ func(has_pxp); \ - func(has_rc6); \ func(has_rc6p); \ func(has_rps); \ func(has_runtime_pm); \
No need to have this parameter in intel_device_info struct as all platforms with graphics version 6 or newer have software support for this feature. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/i915_pci.c | 8 -------- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 2 insertions(+), 10 deletions(-)