| Message ID | 20220508023930.12881-10-suravee.suthikulpanit@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introducing AMD x2AVIC and hybrid-AVIC modes | expand |
On Sat, 2022-05-07 at 21:39 -0500, Suravee Suthikulpanit wrote: > AMD AVIC can support xAPIC and x2APIC virtualization, > which requires changing x2APIC bit VMCB and MSR intercepton > for x2APIC MSRs. Therefore, call avic_refresh_apicv_exec_ctrl() > to refresh configuration accordingly. > > Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> > --- > arch/x86/kvm/svm/avic.c | 12 ++++++++++++ > arch/x86/kvm/svm/svm.c | 1 + > 2 files changed, 13 insertions(+) > > diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c > index 16ce2d50efac..a82981722018 100644 > --- a/arch/x86/kvm/svm/avic.c > +++ b/arch/x86/kvm/svm/avic.c > @@ -691,6 +691,18 @@ void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu) > avic_handle_ldr_update(vcpu); > } > > +void avic_set_virtual_apic_mode(struct kvm_vcpu *vcpu) > +{ > + if (!lapic_in_kernel(vcpu) || (avic_mode == AVIC_MODE_NONE)) > + return; > + > + if (kvm_get_apic_mode(vcpu) == LAPIC_MODE_INVALID) { > + WARN_ONCE(true, "Invalid local APIC state (vcpu_id=%d)", vcpu->vcpu_id); > + return; > + } > + avic_refresh_apicv_exec_ctrl(vcpu); > +} > + > static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) > { > int ret = 0; > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c > index 314628b6bff4..9066568fd19d 100644 > --- a/arch/x86/kvm/svm/svm.c > +++ b/arch/x86/kvm/svm/svm.c > @@ -4692,6 +4692,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { > .enable_nmi_window = svm_enable_nmi_window, > .enable_irq_window = svm_enable_irq_window, > .update_cr8_intercept = svm_update_cr8_intercept, > + .set_virtual_apic_mode = avic_set_virtual_apic_mode, > .refresh_apicv_exec_ctrl = avic_refresh_apicv_exec_ctrl, > .check_apicv_inhibit_reasons = avic_check_apicv_inhibit_reasons, > .apicv_post_state_restore = avic_apicv_post_state_restore, Looks good as well! This code can also be removed in the future as optimization,a and do everything in avic_refresh_apicv_exec_ctrl instead. No need to do this now though. I need to understand the APICv KVM's code better to understand if this is worth it. Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com> Best regards, Maxim Levitsky
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 16ce2d50efac..a82981722018 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -691,6 +691,18 @@ void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu) avic_handle_ldr_update(vcpu); } +void avic_set_virtual_apic_mode(struct kvm_vcpu *vcpu) +{ + if (!lapic_in_kernel(vcpu) || (avic_mode == AVIC_MODE_NONE)) + return; + + if (kvm_get_apic_mode(vcpu) == LAPIC_MODE_INVALID) { + WARN_ONCE(true, "Invalid local APIC state (vcpu_id=%d)", vcpu->vcpu_id); + return; + } + avic_refresh_apicv_exec_ctrl(vcpu); +} + static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) { int ret = 0; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 314628b6bff4..9066568fd19d 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4692,6 +4692,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .enable_nmi_window = svm_enable_nmi_window, .enable_irq_window = svm_enable_irq_window, .update_cr8_intercept = svm_update_cr8_intercept, + .set_virtual_apic_mode = avic_set_virtual_apic_mode, .refresh_apicv_exec_ctrl = avic_refresh_apicv_exec_ctrl, .check_apicv_inhibit_reasons = avic_check_apicv_inhibit_reasons, .apicv_post_state_restore = avic_apicv_post_state_restore,
AMD AVIC can support xAPIC and x2APIC virtualization, which requires changing x2APIC bit VMCB and MSR intercepton for x2APIC MSRs. Therefore, call avic_refresh_apicv_exec_ctrl() to refresh configuration accordingly. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> --- arch/x86/kvm/svm/avic.c | 12 ++++++++++++ arch/x86/kvm/svm/svm.c | 1 + 2 files changed, 13 insertions(+)