| Message ID | 20220509044302.27878-4-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MediaTek MT8195 display binding | expand |
On 09/05/2022 06:43, Rex-BC Chen wrote: > From: "Nancy.Lin" <nancy.lin@mediatek.com> > > Add vdosys1 ETHDR definition. > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../display/mediatek/mediatek,ethdr.yaml | 191 ++++++++++++++++++ > 1 file changed, 191 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > new file mode 100644 > index 000000000000..65f22fba9fed > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > @@ -0,0 +1,191 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Ethdr Device Tree Bindings s/Device Tree Bindings// You need to add some description of a device. What is a Ethdr? > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > + - Philipp Zabel <p.zabel@pengutronix.de> > + > +description: > + ETHDR is designed for HDR video and graphics conversion in the external display path. > + It handles multiple HDR input types and performs tone mapping, color space/color > + format conversion, and then combine different layers, output the required HDR or > + SDR signal to the subsequent display path. This engine is composed of two video > + frontends, two graphic frontends, one video backend and a mixer. ETHDR has two > + DMA function blocks, DS and ADL. These two function blocks read the pre-programmed > + registers from DRAM and set them to HW in the v-blanking period. Block does not look like wrapped at 80. > + > +properties: > + compatible: > + items: One item, so no items. > + - const: mediatek,mt8195-disp-ethdr > + > + reg: > + maxItems: 7 > + > + reg-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + > + interrupts: > + maxItems: 1 > + > + iommus: > + description: The compatible property is DMA function blocks. I don't understand this at all. > + Should point to the respective IOMMU block with master port as argument, > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for > + details. Just skip the description, it's same everywhere. > + minItems: 1 > + maxItems: 2 > + > + clocks: > + items: > + - description: mixer clock > + - description: video frontend 0 clock > + - description: video frontend 1 clock > + - description: graphic frontend 0 clock > + - description: graphic frontend 1 clock > + - description: video backend clock > + - description: autodownload and menuload clock > + - description: video frontend 0 async clock > + - description: video frontend 1 async clock > + - description: graphic frontend 0 async clock > + - description: graphic frontend 1 async clock > + - description: video backend async clock > + - description: ethdr top clock > + > + clock-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + - const: vdo_fe0_async > + - const: vdo_fe1_async > + - const: gfx_fe0_async > + - const: gfx_fe1_async > + - const: vdo_be_async > + - const: ethdr_top > + > + power-domains: > + maxItems: 1 > + > + resets: > + items: > + - description: video frontend 0 async reset > + - description: video frontend 1 async reset > + - description: graphic frontend 0 async reset > + - description: graphic frontend 1 async reset > + - description: video backend async reset > + > + reset-names: > + items: > + - const: vdo_fe0_async > + - const: vdo_fe1_async > + - const: gfx_fe0_async > + - const: gfx_fe1_async > + - const: vdo_be_async > + > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: The register of display function block to be set by gce. > + There are 4 arguments in this property, gce node, subsys id, offset and > + register size. The subsys id is defined in the gce header of each chips > + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of > + display function block. > + items: > + items: > + - description: phandle of GCE > + - description: GCE subsys id > + - description: register offset > + - description: register size > + minItems: 7 > + maxItems: 7 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + - resets > + - mediatek,gce-client-reg > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/mt8195-clk.h> > + #include <dt-bindings/gce/mt8195-gce.h> > + #include <dt-bindings/memory/mt8195-memory-port.h> > + #include <dt-bindings/power/mt8195-power.h> > + #include <dt-bindings/reset/mt8195-resets.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + disp_ethdr@1c114000 { No underscores in node name. Generic node names, so display-controller? Best regards, Krzysztof
On Mon, 2022-05-09 at 15:35 +0800, Krzysztof Kozlowski wrote: > On 09/05/2022 06:43, Rex-BC Chen wrote: > > From: "Nancy.Lin" <nancy.lin@mediatek.com> > > > > Add vdosys1 ETHDR definition. > > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> > > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > .../display/mediatek/mediatek,ethdr.yaml | 191 > > ++++++++++++++++++ > > 1 file changed, 191 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y > > aml > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr > > .yaml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr > > .yaml > > new file mode 100644 > > index 000000000000..65f22fba9fed > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr > > .yaml > > @@ -0,0 +1,191 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml*__;Iw!!CTRNKA9wMg0ARbw!0l-uil4PAknmCtuDbYhilIpDVA7jzpoeImD2nUauP75Bx1wg3O7BVgM4gJL1ckoqSq7r0276AvMSgzFjlPAag3Pv4Q$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!0l-uil4PAknmCtuDbYhilIpDVA7jzpoeImD2nUauP75Bx1wg3O7BVgM4gJL1ckoqSq7r0276AvMSgzFjlPCRT1R8yg$ > > > > + > > +title: MediaTek Ethdr Device Tree Bindings > > s/Device Tree Bindings// Hello Krzysztof, Thanks for your review. We will remove "Device Tree Bindings" in next version. > > You need to add some description of a device. What is a Ethdr? > Ethdr device is described in the description section. Do I need to add anything else? > > + > > +maintainers: > > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > > + - Philipp Zabel <p.zabel@pengutronix.de> > > + > > +description: > > + ETHDR is designed for HDR video and graphics conversion in the > > external display path. > > + It handles multiple HDR input types and performs tone mapping, > > color space/color > > + format conversion, and then combine different layers, output the > > required HDR or > > + SDR signal to the subsequent display path. This engine is > > composed of two video > > + frontends, two graphic frontends, one video backend and a mixer. > > ETHDR has two > > + DMA function blocks, DS and ADL. These two function blocks read > > the pre-programmed > > + registers from DRAM and set them to HW in the v-blanking period. > > Block does not look like wrapped at 80. > ok, we will fix this in next version. > > + > > +properties: > > + compatible: > > + items: > > One item, so no items. ok, we will modofy like this: properties: compatible: - const: mediatek,mt8195-disp-ethdr > > > + - const: mediatek,mt8195-disp-ethdr > > + > > + reg: > > + maxItems: 7 > > + > > + reg-names: > > + items: > > + - const: mixer > > + - const: vdo_fe0 > > + - const: vdo_fe1 > > + - const: gfx_fe0 > > + - const: gfx_fe1 > > + - const: vdo_be > > + - const: adl_ds > > + > > + interrupts: > > + maxItems: 1 > > + > > + iommus: > > + description: The compatible property is DMA function blocks. > > I don't understand this at all. > > > + Should point to the respective IOMMU block with master port > > as argument, > > + see > > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for > > + details. > > Just skip the description, it's same everywhere. OK, we will remove the whole description. > > > + minItems: 1 > > + maxItems: 2 > > + > > + clocks: > > + items: > > + - description: mixer clock > > + - description: video frontend 0 clock > > + - description: video frontend 1 clock > > + - description: graphic frontend 0 clock > > + - description: graphic frontend 1 clock > > + - description: video backend clock > > + - description: autodownload and menuload clock > > + - description: video frontend 0 async clock > > + - description: video frontend 1 async clock > > + - description: graphic frontend 0 async clock > > + - description: graphic frontend 1 async clock > > + - description: video backend async clock > > + - description: ethdr top clock > > + > > + clock-names: > > + items: > > + - const: mixer > > + - const: vdo_fe0 > > + - const: vdo_fe1 > > + - const: gfx_fe0 > > + - const: gfx_fe1 > > + - const: vdo_be > > + - const: adl_ds > > + - const: vdo_fe0_async > > + - const: vdo_fe1_async > > + - const: gfx_fe0_async > > + - const: gfx_fe1_async > > + - const: vdo_be_async > > + - const: ethdr_top > > + > > + power-domains: > > + maxItems: 1 > > + > > + resets: > > + items: > > + - description: video frontend 0 async reset > > + - description: video frontend 1 async reset > > + - description: graphic frontend 0 async reset > > + - description: graphic frontend 1 async reset > > + - description: video backend async reset > > + > > + reset-names: > > + items: > > + - const: vdo_fe0_async > > + - const: vdo_fe1_async > > + - const: gfx_fe0_async > > + - const: gfx_fe1_async > > + - const: vdo_be_async > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + description: The register of display function block to be set > > by gce. > > + There are 4 arguments in this property, gce node, subsys id, > > offset and > > + register size. The subsys id is defined in the gce header of > > each chips > > + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the > > register of > > + display function block. > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + minItems: 7 > > + maxItems: 7 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - interrupts > > + - power-domains > > + - resets > > + - mediatek,gce-client-reg > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/clock/mt8195-clk.h> > > + #include <dt-bindings/gce/mt8195-gce.h> > > + #include <dt-bindings/memory/mt8195-memory-port.h> > > + #include <dt-bindings/power/mt8195-power.h> > > + #include <dt-bindings/reset/mt8195-resets.h> > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + disp_ethdr@1c114000 { > > No underscores in node name. Generic node names, so display- > controller? > OK, we will change the node name to ethdr like in dts like this: ethdr0: ethdr@1c114000 { ... } https://patchwork.kernel.org/project/linux-mediatek/patch/20220504091440.2052-26-nancy.lin@mediatek.com/ BRs, Rex > > Best regards, > Krzysztof
On 09/05/2022 10:54, Rex-BC Chen wrote: >>> + soc { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + disp_ethdr@1c114000 { >> >> No underscores in node name. Generic node names, so display- >> controller? >> > > OK, we will change the node name to ethdr like in dts > like this: > ethdr0: ethdr@1c114000 { > ... > } Is "ethdr" a generic name? Is it an abbreviation of "EnergyTrace™ High Dynamic Range"? If yes, it also looks specific to Texas Instruments... Best regards, Krzysztof
Il 09/05/22 12:44, Krzysztof Kozlowski ha scritto: > On 09/05/2022 10:54, Rex-BC Chen wrote: >>>> + soc { >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + >>>> + disp_ethdr@1c114000 { >>> >>> No underscores in node name. Generic node names, so display- >>> controller? >>> >> >> OK, we will change the node name to ethdr like in dts >> like this: >> ethdr0: ethdr@1c114000 { >> ... >> } > > Is "ethdr" a generic name? Is it an abbreviation of "EnergyTrace™ High > Dynamic Range"? If yes, it also looks specific to Texas Instruments... > > Best regards, > Krzysztof That's mediatek-drm, and this refers to the HDR block in the display IP... Though, I have no idea of what "ET" stands for in "ETHDR", so, it would be definitely nice if MediaTek can write the meaning in the description, like description: ETHDR (E??? T??? High Dynamic Range) is designed for HDR video and ...blah Cheers, Angelo
On Mon, 09 May 2022 12:43:02 +0800, Rex-BC Chen wrote: > From: "Nancy.Lin" <nancy.lin@mediatek.com> > > Add vdosys1 ETHDR definition. > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../display/mediatek/mediatek,ethdr.yaml | 191 ++++++++++++++++++ > 1 file changed, 191 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dts:26:18: fatal error: dt-bindings/memory/mt8195-memory-port.h: No such file or directory 26 | #include <dt-bindings/memory/mt8195-memory-port.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1401: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Mon, 2022-05-09 at 18:50 +0800, AngeloGioacchino Del Regno wrote: > Il 09/05/22 12:44, Krzysztof Kozlowski ha scritto: > > On 09/05/2022 10:54, Rex-BC Chen wrote: > > > > > + soc { > > > > > + #address-cells = <2>; > > > > > + #size-cells = <2>; > > > > > + > > > > > + disp_ethdr@1c114000 { > > > > > > > > No underscores in node name. Generic node names, so display- > > > > controller? > > > > > > > > > > OK, we will change the node name to ethdr like in dts > > > like this: > > > ethdr0: ethdr@1c114000 { > > > ... > > > } > > > > Is "ethdr" a generic name? Is it an abbreviation of "EnergyTrace™ > > High > > Dynamic Range"? If yes, it also looks specific to Texas > > Instruments... > > > > Best regards, > > Krzysztof > > > That's mediatek-drm, and this refers to the HDR block in the display > IP... > > Though, I have no idea of what "ET" stands for in "ETHDR", so, it > would be > definitely nice if MediaTek can write the meaning in the description, > like > > description: > ETHDR (E??? T??? High Dynamic Range) is designed for HDR video and > ...blah > > Cheers, > Angelo Hello Krzysztof and Angelo, "ET" is actually meaningless. ET is one of mediatek departments and it's where the engine from. Therefore, I think we will add description like this: > ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and > designed for HDR video... BRs, Rex
On 10/05/2022 03:46, Rex-BC Chen wrote: >> >> >> That's mediatek-drm, and this refers to the HDR block in the display >> IP... >> >> Though, I have no idea of what "ET" stands for in "ETHDR", so, it >> would be >> definitely nice if MediaTek can write the meaning in the description, >> like >> >> description: >> ETHDR (E??? T??? High Dynamic Range) is designed for HDR video and >> ...blah >> >> Cheers, >> Angelo > > Hello Krzysztof and Angelo, > > "ET" is actually meaningless. > ET is one of mediatek departments and it's where the engine from. > Therefore, I think we will add description like this: >> ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and >> designed for HDR video... Sure, sounds good, but then the node name should not have it. Please try to find some more generic name (DT spec gives examples). Could be display-controller, "hdr-engine", "isp". Best regards, Krzysztof
On Tue, 2022-05-10 at 19:19 +0800, Krzysztof Kozlowski wrote: > On 10/05/2022 03:46, Rex-BC Chen wrote: > > > > > > > > > That's mediatek-drm, and this refers to the HDR block in the > > > display > > > IP... > > > > > > Though, I have no idea of what "ET" stands for in "ETHDR", so, it > > > would be > > > definitely nice if MediaTek can write the meaning in the > > > description, > > > like > > > > > > description: > > > ETHDR (E??? T??? High Dynamic Range) is designed for HDR video > > > and > > > ...blah > > > > > > Cheers, > > > Angelo > > > > Hello Krzysztof and Angelo, > > > > "ET" is actually meaningless. > > ET is one of mediatek departments and it's where the engine from. > > Therefore, I think we will add description like this: > > > ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine > > > and > > > designed for HDR video... > > Sure, sounds good, but then the node name should not have it. Please > try > to find some more generic name (DT spec gives examples). Could be > display-controller, "hdr-engine", "isp". > > > Best regards, > Krzysztof Hello Krzysztof, Thanks for your suggestion. We will use hdr-engine to name this node. Thanks! BRs, Rex
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml new file mode 100644 index 000000000000..65f22fba9fed --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Ethdr Device Tree Bindings + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Philipp Zabel <p.zabel@pengutronix.de> + +description: + ETHDR is designed for HDR video and graphics conversion in the external display path. + It handles multiple HDR input types and performs tone mapping, color space/color + format conversion, and then combine different layers, output the required HDR or + SDR signal to the subsequent display path. This engine is composed of two video + frontends, two graphic frontends, one video backend and a mixer. ETHDR has two + DMA function blocks, DS and ADL. These two function blocks read the pre-programmed + registers from DRAM and set them to HW in the v-blanking period. + +properties: + compatible: + items: + - const: mediatek,mt8195-disp-ethdr + + reg: + maxItems: 7 + + reg-names: + items: + - const: mixer + - const: vdo_fe0 + - const: vdo_fe1 + - const: gfx_fe0 + - const: gfx_fe1 + - const: vdo_be + - const: adl_ds + + interrupts: + maxItems: 1 + + iommus: + description: The compatible property is DMA function blocks. + Should point to the respective IOMMU block with master port as argument, + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for + details. + minItems: 1 + maxItems: 2 + + clocks: + items: + - description: mixer clock + - description: video frontend 0 clock + - description: video frontend 1 clock + - description: graphic frontend 0 clock + - description: graphic frontend 1 clock + - description: video backend clock + - description: autodownload and menuload clock + - description: video frontend 0 async clock + - description: video frontend 1 async clock + - description: graphic frontend 0 async clock + - description: graphic frontend 1 async clock + - description: video backend async clock + - description: ethdr top clock + + clock-names: + items: + - const: mixer + - const: vdo_fe0 + - const: vdo_fe1 + - const: gfx_fe0 + - const: gfx_fe1 + - const: vdo_be + - const: adl_ds + - const: vdo_fe0_async + - const: vdo_fe1_async + - const: gfx_fe0_async + - const: gfx_fe1_async + - const: vdo_be_async + - const: ethdr_top + + power-domains: + maxItems: 1 + + resets: + items: + - description: video frontend 0 async reset + - description: video frontend 1 async reset + - description: graphic frontend 0 async reset + - description: graphic frontend 1 async reset + - description: video backend async reset + + reset-names: + items: + - const: vdo_fe0_async + - const: vdo_fe1_async + - const: gfx_fe0_async + - const: gfx_fe1_async + - const: vdo_be_async + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: The register of display function block to be set by gce. + There are 4 arguments in this property, gce node, subsys id, offset and + register size. The subsys id is defined in the gce header of each chips + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of + display function block. + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + minItems: 7 + maxItems: 7 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - resets + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + #include <dt-bindings/power/mt8195-power.h> + #include <dt-bindings/reset/mt8195-resets.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + disp_ethdr@1c114000 { + compatible = "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11b000 0 0x1000>; + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", + "ethdr_top"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; + reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", + "gfx_fe1_async", "vdo_be_async"; + }; + }; +...