Message ID | 20220504184850.24986-2-alisaidi@amazon.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | perf: arm-spe: Decode SPE source and use for perf c2c | expand |
On 5/5/22 00:18, Ali Saidi wrote: > Add a flag to the perf mem data struct to signal that a request caused a > cache-to-cache transfer of a line from a peer of the requestor and > wasn't sourced from a lower cache level. The line being moved from one > peer cache to another has latency and performance implications. On Arm64 > Neoverse systems the data source can indicate a cache-to-cache transfer > but not if the line is dirty or clean, so instead of overloading HITM > define a new flag that indicates this type of transfer. > > Signed-off-by: Ali Saidi <alisaidi@amazon.com> > Reviewed-by: Leo Yan <leo.yan@linaro.org> > --- > include/uapi/linux/perf_event.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h > index d37629dbad72..7b88bfd097dc 100644 > --- a/include/uapi/linux/perf_event.h > +++ b/include/uapi/linux/perf_event.h > @@ -1310,7 +1310,7 @@ union perf_mem_data_src { > #define PERF_MEM_SNOOP_SHIFT 19 > > #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ > -/* 1 free */ > +#define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ > #define PERF_MEM_SNOOPX_SHIFT 38 > > /* locked instruction */ Patch looks good to me. Reviewed-By: Kajol Jain<kjain@linux.ibm.com> Thanks, Kajol Jain
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index d37629dbad72..7b88bfd097dc 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -1310,7 +1310,7 @@ union perf_mem_data_src { #define PERF_MEM_SNOOP_SHIFT 19 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ -/* 1 free */ +#define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ #define PERF_MEM_SNOOPX_SHIFT 38 /* locked instruction */