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[RESEND,02/10] target/ppc: Move mffs[.] to decodetree

Message ID 20220517164744.58131-3-victor.colombo@eldorado.org.br (mailing list archive)
State New, archived
Headers show
Series BCDA and mffscdrn implementations | expand

Commit Message

Víctor Colombo May 17, 2022, 4:47 p.m. UTC 
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
 target/ppc/insn32.decode           |  7 +++++++
 target/ppc/translate/fp-impl.c.inc | 25 +++++++++++++++++++++++++
 target/ppc/translate/fp-ops.c.inc  |  1 -
 3 files changed, 32 insertions(+), 1 deletion(-)

Comments

Richard Henderson May 17, 2022, 6:30 p.m. UTC | #1 
On 5/17/22 09:47, Víctor Colombo wrote:
> index cfb27bd020..e167f7a478 100644
> --- a/target/ppc/translate/fp-impl.c.inc
> +++ b/target/ppc/translate/fp-impl.c.inc
> @@ -607,6 +607,31 @@ static void gen_mffs(DisasContext *ctx)
>       tcg_temp_free_i64(t0);
>   }
>   
> +static void do_mffsc(int rt)

Perhaps cleaner to introduce set_mask straight away.  However,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
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Patch

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b47213764d..a6e1337c51 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -94,6 +94,9 @@ 
 &X_tb           rt rb
 @X_tb           ...... rt:5 ..... rb:5 .......... .             &X_tb
 
+&X_t_rc         rt rc:bool
+@X_t_rc         ...... rt:5 ..... ..... .......... rc:1         &X_t_rc
+
 &X_tb_rc        rt rb rc:bool
 @X_tb_rc        ...... rt:5 ..... rb:5 .......... rc:1          &X_tb_rc
 
@@ -315,6 +318,10 @@  SETBCR          011111 ..... ..... ----- 0110100000 -   @X_bi
 SETNBC          011111 ..... ..... ----- 0111000000 -   @X_bi
 SETNBCR         011111 ..... ..... ----- 0111100000 -   @X_bi
 
+### Move To/From FPSCR
+
+MFFS            111111 ..... 00000 ----- 1001000111 .   @X_t_rc
+
 ### Decimal Floating-Point Arithmetic Instructions
 
 DADD            111011 ..... ..... ..... 0000000010 .   @X_rc
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index cfb27bd020..e167f7a478 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -607,6 +607,31 @@  static void gen_mffs(DisasContext *ctx)
     tcg_temp_free_i64(t0);
 }
 
+static void do_mffsc(int rt)
+{
+    TCGv_i64 fpscr;
+
+    fpscr = tcg_temp_new_i64();
+
+    gen_reset_fpstatus();
+    tcg_gen_extu_tl_i64(fpscr, cpu_fpscr);
+    set_fpr(rt, fpscr);
+
+    tcg_temp_free_i64(fpscr);
+}
+
+static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a)
+{
+    REQUIRE_FPU(ctx);
+
+    do_mffsc(a->rt);
+    if (a->rc) {
+        gen_set_cr1_from_fpscr(ctx);
+    }
+
+    return true;
+}
+
 /* mffsl */
 static void gen_mffsl(DisasContext *ctx)
 {
diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc
index 4260635a12..7aa4011ef3 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -75,7 +75,6 @@  GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
-GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
 GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT,
     PPC2_ISA300),
 GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,