| Message ID | 20220519153107.696864-13-clement.leger@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | add support for Renesas RZ/N1 ethernet subsystem devices | expand |
On Thu, May 19, 2022 at 05:31:06PM +0200, Clément Léger wrote: > Add description of the switch that is present on the RZ/N1 SoC. > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> > --- > arch/arm/boot/dts/r9a06g032.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi > index 31c4b2e2950a..20d3dce632ce 100644 > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -255,6 +255,15 @@ mii_conv5: mii-conv@5 { > }; > }; > > + switch: switch@44050000 { > + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; > + reg = <0x44050000 0x10000>; > + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, > + <&sysctrl R9A06G032_CLK_SWITCH>; > + clock-names = "hclk", "clk"; > + status = "disabled"; Does the switch port count depend on anything? If it doesn't, maybe you could add the "ethernet-ports" node and all the ports here, with status = "disabled", so that board files don't need to spell them out each time? I'm also thinking you could define the fixed-link and phy-mode = "internal" property of the CPU port with this occasion. That surely isn't a per-board thing. > + }; > + > gic: interrupt-controller@44101000 { > compatible = "arm,gic-400", "arm,cortex-a7-gic"; > interrupt-controller; > -- > 2.36.0 >
Le Thu, 19 May 2022 21:28:12 +0300, Vladimir Oltean <olteanv@gmail.com> a écrit : > Does the switch port count depend on anything? If it doesn't, maybe you > could add the "ethernet-ports" node and all the ports here, with status > = "disabled", so that board files don't need to spell them out each time? Port count does not depends on anything, it's always fixed so indeed, it would be a good idea to provide all the ports as disabled. > I'm also thinking you could define the fixed-link and phy-mode = "internal" > property of the CPU port with this occasion. That surely isn't a > per-board thing. Totally. Thanks,
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 31c4b2e2950a..20d3dce632ce 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -255,6 +255,15 @@ mii_conv5: mii-conv@5 { }; }; + switch: switch@44050000 { + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; + reg = <0x44050000 0x10000>; + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, + <&sysctrl R9A06G032_CLK_SWITCH>; + clock-names = "hclk", "clk"; + status = "disabled"; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller;
Add description of the switch that is present on the RZ/N1 SoC. Signed-off-by: Clément Léger <clement.leger@bootlin.com> --- arch/arm/boot/dts/r9a06g032.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)