diff mbox series

[v1,3/6] RISC-V: Remove the unimplemented ISA extensions

Message ID 20220402050041.21302-4-palmer@rivosinc.com (mailing list archive)
State Mainlined, archived
Headers show
Series RISC-V -march handling improvements | expand

Commit Message

Palmer Dabbelt April 2, 2022, 5 a.m. UTC
This made sense when we die()d on unknown ISA extensions, but now that
we're just warning it's actually a bit detrimental: users won't see that
their unimplemented ISA extensions are silently having the wrong
definitions set, which may cause hard to debug failures.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 target-riscv.c | 10 ----------
 1 file changed, 10 deletions(-)

Comments

Luc Van Oostenryck May 21, 2022, 10:05 p.m. UTC | #1
On Fri, Apr 01, 2022 at 10:00:38PM -0700, Palmer Dabbelt wrote:
> This made sense when we die()d on unknown ISA extensions, but now that
> we're just warning it's actually a bit detrimental: users won't see that
> their unimplemented ISA extensions are silently having the wrong
> definitions set, which may cause hard to debug failures.
> 
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
>  target-riscv.c | 10 ----------
>  1 file changed, 10 deletions(-)
> 
> diff --git a/target-riscv.c b/target-riscv.c
> index 494c08db..924259af 100644
> --- a/target-riscv.c
> +++ b/target-riscv.c
> @@ -37,17 +37,7 @@ static void parse_march_riscv(const char *arg)
>  		{ "f",		RISCV_FLOAT|RISCV_FDIV },
>  		{ "d",		RISCV_DOUBLE|RISCV_FDIV },
>  		{ "g",		RISCV_GENERIC },
> -		{ "q",		0 },
> -		{ "l",		0 },
>  		{ "c",		RISCV_COMP },
> -		{ "b",		0 },
> -		{ "j",		0 },
> -		{ "t",		0 },
> -		{ "p",		0 },
> -		{ "v",		0 },
> -		{ "n",		0 },
> -		{ "h",		0 },
> -		{ "s",		0 },

OK, it seems than most of them have anyway no chances to be officialized
anytime soon. Maybe just add the define for p & v together with
the Zb* ones when switching __riscv_arch_test).

-- Luc
diff mbox series

Patch

diff --git a/target-riscv.c b/target-riscv.c
index 494c08db..924259af 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -37,17 +37,7 @@  static void parse_march_riscv(const char *arg)
 		{ "f",		RISCV_FLOAT|RISCV_FDIV },
 		{ "d",		RISCV_DOUBLE|RISCV_FDIV },
 		{ "g",		RISCV_GENERIC },
-		{ "q",		0 },
-		{ "l",		0 },
 		{ "c",		RISCV_COMP },
-		{ "b",		0 },
-		{ "j",		0 },
-		{ "t",		0 },
-		{ "p",		0 },
-		{ "v",		0 },
-		{ "n",		0 },
-		{ "h",		0 },
-		{ "s",		0 },
 	};
 	int i;