| Message ID | 20220526084240.31298-1-nikita.shubin@maquefel.me (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: fix priv enum | expand |
On Thu, May 26, 2022 at 2:15 PM Nikita Shubin <nikita.shubin@maquefel.me> wrote: > > From: Nikita Shubin <n.shubin@yadro.com> > > Add PRIV_VERSION_UNKNOWN to enum, otherwise PRIV_VERSION_1_10_0 will > be overwritten to PRIV_VERSION_1_12_0 in riscv_cpu_realize. > > Fixes: a46d410c5c ("target/riscv: Define simpler privileged spec version numbering") > Signed-off-by: Nikita Shubin <n.shubin@yadro.com> This breaks the CSR ops table because with this patch most CSRs (not having explicit min_priv_version value) will be associated with an unknown priv spec version. Please check "[PATCH v3 1/4] target/riscv: Don't force update priv spec version to latest" which I just sent. Thanks, Anup > --- > target/riscv/cpu.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f08c3e8813..1f1d6589a7 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -91,7 +91,8 @@ enum { > > /* Privileged specification version */ > enum { > - PRIV_VERSION_1_10_0 = 0, > + PRIV_VERSION_UNKNOWN = 0, > + PRIV_VERSION_1_10_0, > PRIV_VERSION_1_11_0, > PRIV_VERSION_1_12_0, > }; > -- > 2.35.1 > >
Hi Anup! On Thu, 26 May 2022 15:37:54 +0530 Anup Patel <anup@brainfault.org> wrote: > On Thu, May 26, 2022 at 2:15 PM Nikita Shubin > <nikita.shubin@maquefel.me> wrote: > > > > From: Nikita Shubin <n.shubin@yadro.com> > > > > Add PRIV_VERSION_UNKNOWN to enum, otherwise PRIV_VERSION_1_10_0 will > > be overwritten to PRIV_VERSION_1_12_0 in riscv_cpu_realize. > > > > Fixes: a46d410c5c ("target/riscv: Define simpler privileged spec > > version numbering") Signed-off-by: Nikita Shubin > > <n.shubin@yadro.com> > > This breaks the CSR ops table because with this patch most CSRs > (not having explicit min_priv_version value) will be associated with > an unknown priv spec version. > > Please check "[PATCH v3 1/4] target/riscv: Don't force update priv > spec version to latest" which I just sent. Makes sense, thank you pointing it out. > > Thanks, > Anup > > > > --- > > target/riscv/cpu.h | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index f08c3e8813..1f1d6589a7 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -91,7 +91,8 @@ enum { > > > > /* Privileged specification version */ > > enum { > > - PRIV_VERSION_1_10_0 = 0, > > + PRIV_VERSION_UNKNOWN = 0, > > + PRIV_VERSION_1_10_0, > > PRIV_VERSION_1_11_0, > > PRIV_VERSION_1_12_0, > > }; > > -- > > 2.35.1 > > > >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f08c3e8813..1f1d6589a7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -91,7 +91,8 @@ enum { /* Privileged specification version */ enum { - PRIV_VERSION_1_10_0 = 0, + PRIV_VERSION_UNKNOWN = 0, + PRIV_VERSION_1_10_0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, };