| Message ID | 20220506191339.78617-1-nick.hawkins@hpe.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce HPE GXP Architecture | expand |
Hi! > From: Nick Hawkins <nick.hawkins@hpe.com> > > The GXP is the HPE BMC SoC that is used in the majority > of current generation HPE servers. Traditionally the asic will > last multiple generations of server before being replaced. > > Info about SoC: Normally, 1/7 goes into the same thread as 0/7 mail. Best regards, Pavel
> > From: Nick Hawkins <nick.hawkins@hpe.com> > > > > The GXP is the HPE BMC SoC that is used in the majority of current > > generation HPE servers. Traditionally the asic will last multiple > > generations of server before being replaced. > > > > Info about SoC: > Normally, 1/7 goes into the same thread as 0/7 mail. Hello Pavel, Thank you for the feedback. I believe the code is already in the process of being merged upstream in version v8. For future reference can you elaborate on what you mean? Thanks, -Nick Hawkins
On Wed 2022-06-01 14:14:33, Hawkins, Nick wrote: > > > From: Nick Hawkins <nick.hawkins@hpe.com> > > > > > > The GXP is the HPE BMC SoC that is used in the majority of current > > > generation HPE servers. Traditionally the asic will last multiple > > > generations of server before being replaced. > > > > > > Info about SoC: > > > Normally, 1/7 goes into the same thread as 0/7 mail. > > Hello Pavel, > > Thank you for the feedback. I believe the code is already in the process of being merged upstream in version v8. For future reference can you elaborate on what you mean? > You used separate email threads for 0/7 and the rest of the patches. Normally, they should go to single email thread. Best regards, Pavel
On Wed, Jun 1, 2022 at 10:57 PM Pavel Machek <pavel@ucw.cz> wrote: > On Wed 2022-06-01 14:14:33, Hawkins, Nick wrote: > > > > From: Nick Hawkins <nick.hawkins@hpe.com> > > > > > > > > The GXP is the HPE BMC SoC that is used in the majority of current > > > > generation HPE servers. Traditionally the asic will last multiple > > > > generations of server before being replaced. > > > > > > > > Info about SoC: > > > > > Normally, 1/7 goes into the same thread as 0/7 mail. > > > > Hello Pavel, > > > > Thank you for the feedback. I believe the code is already in the process of being merged upstream in version v8. For future reference can you elaborate on what you mean? > > > > You used separate email threads for 0/7 and the rest of the > patches. Normally, they should go to single email thread. > To clarify: the way this is normally done is to prepare the series using 'git format-patch --cover-letter ...' and then send it using 'git send-email --thread --no-chain-reply', which makes all patches a reply to the cover letter. Arnd
> To clarify: the way this is normally done is to prepare the series using 'git format-patch --cover-letter ...' and then send it using 'git send-email --thread --no-chain-reply', which makes all patches a reply to the cover letter.
I see thank you for the information! I will be sure to use this on future patch sets.
-Nick Hawkins
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e8091e2d8a8..13f77eec7c40 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -620,6 +620,8 @@ source "arch/arm/mach-highbank/Kconfig" source "arch/arm/mach-hisi/Kconfig" +source "arch/arm/mach-hpe/Kconfig" + source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-integrator/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a2391b8de5a5..97a89023c10f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -179,6 +179,7 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi +machine-$(CONFIG_ARCH_HPE) += hpe machine-$(CONFIG_ARCH_INTEGRATOR) += integrator machine-$(CONFIG_ARCH_IOP32X) += iop32x machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx diff --git a/arch/arm/mach-hpe/Kconfig b/arch/arm/mach-hpe/Kconfig new file mode 100644 index 000000000000..3372bbf38d38 --- /dev/null +++ b/arch/arm/mach-hpe/Kconfig @@ -0,0 +1,23 @@ +menuconfig ARCH_HPE + bool "HPE SoC support" + depends on ARCH_MULTI_V7 + help + This enables support for HPE ARM based BMC chips. +if ARCH_HPE + +config ARCH_HPE_GXP + bool "HPE GXP SoC" + depends on ARCH_MULTI_V7 + select ARM_VIC + select GENERIC_IRQ_CHIP + select CLKSRC_MMIO + help + HPE GXP is the name of the HPE Soc. This SoC is used to implement many + BMC features at HPE. It supports ARMv7 architecture based on the Cortex + A9 core. It is capable of using an AXI bus to which a memory controller + is attached. It has multiple SPI interfaces to connect boot flash and + BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It + has multiple i2c engines to drive connectivity with a host + infrastructure. + +endif diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile new file mode 100644 index 000000000000..8b0a91234df4 --- /dev/null +++ b/arch/arm/mach-hpe/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_HPE_GXP) += gxp.o diff --git a/arch/arm/mach-hpe/gxp.c b/arch/arm/mach-hpe/gxp.c new file mode 100644 index 000000000000..ef3341373006 --- /dev/null +++ b/arch/arm/mach-hpe/gxp.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */ + +#include <linux/of_platform.h> +#include <asm/mach/arch.h> + +static const char * const gxp_board_dt_compat[] = { + "hpe,gxp", + NULL, +}; + +DT_MACHINE_START(GXP_DT, "HPE GXP") + .dt_compat = gxp_board_dt_compat, + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, +MACHINE_END