Message ID | 20220424090216.21887-1-mchitale@ventanamicro.com (mailing list archive) |
---|---|
Headers | show |
Series | Risc-V Svinval support | expand |
On Sun, 24 Apr 2022 02:02:14 PDT (-0700), mchitale@ventanamicro.com wrote: > > This patch adds support for the Svinval extension as defined in the > Risc V Privileged specification. This patchset depends on: > > https://patchwork.kernel.org/project/linux-riscv/list/?series=632984 IIRC Marc still has some unresolved feedback on that one, for the IRQ bits? > > The feature was tested with qemu from latest master branch with > following additional patch: > https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00142.html > > Changes in V2: > > - Rebased on 5.18-rc3 > - update riscv_fill_hwcap to probe Svinval extension > > Mayuresh Chitale (2): > riscv: enum for svinval extension > riscv: mm: use svinval instructions instead of sfence.vma > > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/tlbflush.h | 12 ++++ > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > arch/riscv/kernel/setup.c | 1 + > arch/riscv/mm/tlbflush.c | 116 ++++++++++++++++++++++++++++-- > 6 files changed, 126 insertions(+), 6 deletions(-)