| Message ID | 20220530180328.845692-1-fparent@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC | expand |
On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote: > Add IOMMU binding documentation for the MT8365 SoC. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > --- > .../bindings/iommu/mediatek,iommu.yaml | 2 + > include/dt-bindings/memory/mt8365-larb-port.h | 96 > +++++++++++++++++++ > 2 files changed, 98 insertions(+) > create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h [snip...] > +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ > +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ > + > +#include <dt-bindings/memory/mtk-memory-port.h> > + > +#define M4U_LARB0_ID 0 > +#define M4U_LARB1_ID 1 > +#define M4U_LARB2_ID 2 > +#define M4U_LARB3_ID 3 > +#define M4U_LARB4_ID 4 > +#define M4U_LARB5_ID 5 > +#define M4U_LARB6_ID 6 > +#define M4U_LARB7_ID 7 Remove these. they are no used, right? > + > +/* larb0 */ > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(0, 1) [...] > > +/* larb4 */ > +#define M4U_PORT_APU_READ MTK_M4U_ID(0, 0) > +#define M4U_PORT_APU_WRITE MTK_M4U_ID(0, 1) Please remove these two APU definitions. currently these are not supported. Thanks. > + > +#endif
On Thu, 2022-06-02 at 16:42 +0800, Macpaul Lin wrote: > On 6/2/22 4:27 PM, Macpaul Lin wrote: > > On 6/2/22 2:18 PM, Yong Wu wrote: > > > On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote: > > > > Add IOMMU binding documentation for the MT8365 SoC. > > > > > > > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > > > > --- > > > > .../bindings/iommu/mediatek,iommu.yaml | 2 + > > > > include/dt-bindings/memory/mt8365-larb-port.h | 96 > > > > +++++++++++++++++++ > > > > 2 files changed, 98 insertions(+) > > > > create mode 100644 include/dt-bindings/memory/mt8365-larb- > > > > port.h > > > > > > [snip...] > > > > > > > +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ > > > > +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ > > > > + > > > > +#include <dt-bindings/memory/mtk-memory-port.h> > > > > + > > > > +#define M4U_LARB0_ID 0 > > > > +#define M4U_LARB1_ID 1 > > > > +#define M4U_LARB2_ID 2 > > > > +#define M4U_LARB3_ID 3 > > > > +#define M4U_LARB4_ID 4 > > > > +#define M4U_LARB5_ID 5 > > > > +#define M4U_LARB6_ID 6 > > > > +#define M4U_LARB7_ID 7 > > > > > > Remove these. they are no used, right? > > > > AIOT and customers are using the modules and their related IOMMU > > modules. > > DISP0, VENC, VDEC, ISP (CAMSYS), and APU (as far as I know, which > > should > > be VP6?) were all supported. > > Dear Yong, > How about to replace the following definitions? > > For example, replace > #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) > to > #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID , 0) Yes. It is ok. > > > > > > > > + > > > > +/* larb0 */ > > > > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) > > > > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(0, 1) > > > > > > [...] > > > > > > > > > > > +/* larb4 */ > > > > +#define M4U_PORT_APU_READ MTK_M4U_ID(0, 0) > > > > +#define M4U_PORT_APU_WRITE MTK_M4U_ID(0, 1) > > > > > > Please remove these two APU definitions. currently these are not > > > supported. > > > > Kidd, please help to check if APU use these definitions with Yong. > > However, I think these are all available to the customers. > > > > Thanks > > Macpaul Lin > > Thanks > Macpaul Lin
On Mon, May 30, 2022 at 08:03:26PM +0200, Fabien Parent wrote: > Add IOMMU binding documentation for the MT8365 SoC. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > --- > .../bindings/iommu/mediatek,iommu.yaml | 2 + > include/dt-bindings/memory/mt8365-larb-port.h | 96 +++++++++++++++++++ > 2 files changed, 98 insertions(+) > create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > index 97e8c471a5e8..5ba688365da5 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > @@ -77,6 +77,7 @@ properties: > - mediatek,mt8173-m4u # generation two > - mediatek,mt8183-m4u # generation two > - mediatek,mt8192-m4u # generation two > + - mediatek,mt8365-m4u # generation two > > - description: mt7623 generation one > items: > @@ -120,6 +121,7 @@ properties: > dt-binding/memory/mt8173-larb-port.h for mt8173, > dt-binding/memory/mt8183-larb-port.h for mt8183, > dt-binding/memory/mt8192-larb-port.h for mt8192. > + dt-binding/memory/mt8365-larb-port.h for mt8365. > > power-domains: > maxItems: 1 > diff --git a/include/dt-bindings/memory/mt8365-larb-port.h b/include/dt-bindings/memory/mt8365-larb-port.h > new file mode 100644 > index 000000000000..e7d5637aa38e > --- /dev/null > +++ b/include/dt-bindings/memory/mt8365-larb-port.h > @@ -0,0 +1,96 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Dual license please. Rob
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 97e8c471a5e8..5ba688365da5 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -77,6 +77,7 @@ properties: - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two - mediatek,mt8192-m4u # generation two + - mediatek,mt8365-m4u # generation two - description: mt7623 generation one items: @@ -120,6 +121,7 @@ properties: dt-binding/memory/mt8173-larb-port.h for mt8173, dt-binding/memory/mt8183-larb-port.h for mt8183, dt-binding/memory/mt8192-larb-port.h for mt8192. + dt-binding/memory/mt8365-larb-port.h for mt8365. power-domains: maxItems: 1 diff --git a/include/dt-bindings/memory/mt8365-larb-port.h b/include/dt-bindings/memory/mt8365-larb-port.h new file mode 100644 index 000000000000..e7d5637aa38e --- /dev/null +++ b/include/dt-bindings/memory/mt8365-larb-port.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 +#define M4U_LARB4_ID 4 +#define M4U_LARB5_ID 5 +#define M4U_LARB6_ID 6 +#define M4U_LARB7_ID 7 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(0, 1) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(0, 2) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(0, 3) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(0, 4) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(0, 5) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(0, 6) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(0, 7) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(0, 8) +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(0, 9) + +/* larb1 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(1, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(1, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(1, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(1, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(1, 4) +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(1, 5) +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(1, 6) +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(1, 7) +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(1, 8) +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(1, 9) +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(1, 10) +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(1, 11) +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(1, 12) +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(1, 13) +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(1, 14) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(1, 15) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(1, 16) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(1, 17) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(1, 18) + +/* larb2 */ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(2, 0) +#define M4U_PORT_CAM_RRZO MTK_M4U_ID(2, 1) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(2, 2) +#define M4U_PORT_CAM_LCS MTK_M4U_ID(2, 3) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(2, 4) +#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(2, 5) +#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(2, 6) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(2, 7) +#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(2, 8) +#define M4U_PORT_CAM_AFO MTK_M4U_ID(2, 9) +#define M4U_PORT_CAM_SPARE MTK_M4U_ID(2, 10) +#define M4U_PORT_CAM_BPCI MTK_M4U_ID(2, 11) +#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(2, 12) +#define M4U_PORT_CAM_UFDI MTK_M4U_ID(2, 13) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(2, 14) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(2, 15) +#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(2, 16) +#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(2, 17) +#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(2, 18) +#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(2, 19) +#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(2, 20) +#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(2, 21) +#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(2, 22) +#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(2, 23) + +/* larb3 */ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(3, 0) +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(3, 1) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(3, 2) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(3, 3) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(3, 4) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(3, 5) +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(3, 6) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(3, 7) +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(3, 8) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(3, 9) +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(3, 10) + +/* larb4 */ +#define M4U_PORT_APU_READ MTK_M4U_ID(0, 0) +#define M4U_PORT_APU_WRITE MTK_M4U_ID(0, 1) + +#endif
Add IOMMU binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> --- .../bindings/iommu/mediatek,iommu.yaml | 2 + include/dt-bindings/memory/mt8365-larb-port.h | 96 +++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h