| Message ID | 20220531012220.80563-3-alim.akhtar@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for UFS controller found in FSD SoC | expand |
On 31/05/2022 03:22, Alim Akhtar wrote: > Move CDR lock offset to drv data so that it can > be extended for other SoCs which are having CDR > lock at different register offset. > > Cc: linux-fsd@tesla.com > Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com> > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> > --- > drivers/phy/samsung/phy-exynos7-ufs.c | 3 +++ > drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++ > drivers/phy/samsung/phy-samsung-ufs.c | 3 ++- > drivers/phy/samsung/phy-samsung-ufs.h | 2 +- > 4 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c > index 7c9008e163db..d1a37273cb1f 100644 > --- a/drivers/phy/samsung/phy-exynos7-ufs.c > +++ b/drivers/phy/samsung/phy-exynos7-ufs.c > @@ -11,6 +11,8 @@ > #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 > #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) > > +#define PHY_CDR_LOCK_STATUS 0x5e This should be now renamed to match other defines here, so EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS Best regards, Krzysztof
On 31/05/2022 03:22, Alim Akhtar wrote: > Move CDR lock offset to drv data so that it can > be extended for other SoCs which are having CDR > lock at different register offset. Line wrapping is too early https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586 Best regards, Krzysztof
>-----Original Message----- >From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@linaro.org] >Sent: Tuesday, May 31, 2022 3:26 PM >To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm- >kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux- >scsi@vger.kernel.org; linux-phy@lists.infradead.org >Cc: devicetree@vger.kernel.org; robh+dt@kernel.org; >krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com; >bvanassche@acm.org; martin.petersen@oracle.com; >chanho61.park@samsung.com; pankaj.dubey@samsung.com; linux- >fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com> >Subject: Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata > >On 31/05/2022 03:22, Alim Akhtar wrote: >> Move CDR lock offset to drv data so that it can be extended for other >> SoCs which are having CDR lock at different register offset. >> >> Cc: linux-fsd@tesla.com >> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> >> --- >> drivers/phy/samsung/phy-exynos7-ufs.c | 3 +++ >> drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++ >> drivers/phy/samsung/phy-samsung-ufs.c | 3 ++- >> drivers/phy/samsung/phy-samsung-ufs.h | 2 +- >> 4 files changed, 8 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c >> b/drivers/phy/samsung/phy-exynos7-ufs.c >> index 7c9008e163db..d1a37273cb1f 100644 >> --- a/drivers/phy/samsung/phy-exynos7-ufs.c >> +++ b/drivers/phy/samsung/phy-exynos7-ufs.c >> @@ -11,6 +11,8 @@ >> #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 >> #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) >> >> +#define PHY_CDR_LOCK_STATUS 0x5e > >This should be now renamed to match other defines here, so >EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS > Sure, will update in next version > >Best regards, >Krzysztof
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c index 7c9008e163db..d1a37273cb1f 100644 --- a/drivers/phy/samsung/phy-exynos7-ufs.c +++ b/drivers/phy/samsung/phy-exynos7-ufs.c @@ -11,6 +11,8 @@ #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define PHY_CDR_LOCK_STATUS 0x5e + /* Calibration for phy initialization */ static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = { PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), @@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = { .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN, }, .has_symbol_clk = 1, + .cdr_lock_status_offset = PHY_CDR_LOCK_STATUS, }; diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c index 36398a15c2db..1572b985c70d 100644 --- a/drivers/phy/samsung/phy-exynosautov9-ufs.c +++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c @@ -10,6 +10,7 @@ #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \ PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) @@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = { .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN, }, .has_symbol_clk = 0, + .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, }; diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c index 602ddef259eb..8e5ae228daa7 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.c +++ b/drivers/phy/samsung/phy-samsung-ufs.c @@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy) } err = readl_poll_timeout( - ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS), + ufs_phy->reg_pma + + PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset), val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us); if (err) dev_err(ufs_phy->dev, diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h index 91a0e9f94f98..965c79bbc278 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.h +++ b/drivers/phy/samsung/phy-samsung-ufs.h @@ -40,7 +40,6 @@ /* UFS PHY registers */ #define PHY_PLL_LOCK_STATUS 0x1e -#define PHY_CDR_LOCK_STATUS 0x5e #define PHY_PLL_LOCK_BIT BIT(5) #define PHY_CDR_LOCK_BIT BIT(4) @@ -109,6 +108,7 @@ struct samsung_ufs_phy_drvdata { u32 en; } isol; bool has_symbol_clk; + u32 cdr_lock_status_offset; }; struct samsung_ufs_phy {