diff mbox series

[v3,20/21] pinctrl: renesas: r8a779g0: add missing MODSELx for TSN0

Message ID 87bkuvkcmi.wl-kuninori.morimoto.gx@renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series pinctrl: renesas: r8a779g0: Add pins, groups and functions | expand

Commit Message

Kuninori Morimoto June 14, 2022, 6 a.m. UTC 
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

TSN0 needs MODSEL4 settings.
This patch adds missing MODSELx setting for these.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 drivers/pinctrl/renesas/pfc-r8a779g0.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

Comments

Geert Uytterhoeven June 17, 2022, 3:19 p.m. UTC | #1 
Hi Morimoto-san,

On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> TSN0 needs MODSEL4 settings.
> This patch adds missing MODSELx setting for these.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Thanks for your patch!

> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -720,27 +720,30 @@ static const u16 pinmux_data[] = {
>         PINMUX_SINGLE(AVS0),
>         PINMUX_SINGLE(PCIE1_CLKREQ_N),
>         PINMUX_SINGLE(PCIE0_CLKREQ_N),
> +
> +       /* TSN0 without MDSEL4 */

MODSEL4

>         PINMUX_SINGLE(TSN0_TXCREFCLK),
> -       PINMUX_SINGLE(TSN0_TD2),
> -       PINMUX_SINGLE(TSN0_TD3),
>         PINMUX_SINGLE(TSN0_RD2),
>         PINMUX_SINGLE(TSN0_RD3),
> -       PINMUX_SINGLE(TSN0_TD0),
> -       PINMUX_SINGLE(TSN0_TD1),
>         PINMUX_SINGLE(TSN0_RD1),
> -       PINMUX_SINGLE(TSN0_TXC),
>         PINMUX_SINGLE(TSN0_RXC),
>         PINMUX_SINGLE(TSN0_RD0),
> -       PINMUX_SINGLE(TSN0_TX_CTL),
> -       PINMUX_SINGLE(TSN0_AVTP_PPS0),
>         PINMUX_SINGLE(TSN0_RX_CTL),
>         PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
> -       PINMUX_SINGLE(TSN0_AVTP_MATCH),
>         PINMUX_SINGLE(TSN0_LINK),
>         PINMUX_SINGLE(TSN0_PHY_INT),
> -       PINMUX_SINGLE(TSN0_AVTP_PPS1),
> -       PINMUX_SINGLE(TSN0_MDC),
>         PINMUX_SINGLE(TSN0_MDIO),
> +       /* TSN0 with MDSEL4 */

MODSEL4

> +       PINMUX_IPSR_NOGM(0, TSN0_TD2,           SEL_TSN0_TD2_1),
> +       PINMUX_IPSR_NOGM(0, TSN0_TD3,           SEL_TSN0_TD3_1),
> +       PINMUX_IPSR_NOGM(0, TSN0_TD0,           SEL_TSN0_TD0_1),
> +       PINMUX_IPSR_NOGM(0, TSN0_TD1,           SEL_TSN0_TD1_1),
> +       PINMUX_IPSR_NOGM(0, TSN0_TXC,           SEL_TSN0_TXC_1),
> +       PINMUX_IPSR_NOGM(0, TSN0_TX_CTL,        SEL_TSN0_TX_CTL_1),
> +       PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS0,     SEL_TSN0_AVTP_PPS0_1),
> +       PINMUX_IPSR_NOGM(0, TSN0_AVTP_MATCH,    SEL_TSN0_AVTP_MATCH_1),
> +       PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1,     SEL_TSN0_AVTP_PPS1_1),
> +       PINMUX_IPSR_NOGM(0, TSN0_MDC,           SEL_TSN0_MDC_1),
>
>         PINMUX_SINGLE(AVB2_RX_CTL),
>         PINMUX_SINGLE(AVB2_TX_CTL),

With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 06a1b08a3cb7..c96d95907972 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -720,27 +720,30 @@  static const u16 pinmux_data[] = {
 	PINMUX_SINGLE(AVS0),
 	PINMUX_SINGLE(PCIE1_CLKREQ_N),
 	PINMUX_SINGLE(PCIE0_CLKREQ_N),
+
+	/* TSN0 without MDSEL4 */
 	PINMUX_SINGLE(TSN0_TXCREFCLK),
-	PINMUX_SINGLE(TSN0_TD2),
-	PINMUX_SINGLE(TSN0_TD3),
 	PINMUX_SINGLE(TSN0_RD2),
 	PINMUX_SINGLE(TSN0_RD3),
-	PINMUX_SINGLE(TSN0_TD0),
-	PINMUX_SINGLE(TSN0_TD1),
 	PINMUX_SINGLE(TSN0_RD1),
-	PINMUX_SINGLE(TSN0_TXC),
 	PINMUX_SINGLE(TSN0_RXC),
 	PINMUX_SINGLE(TSN0_RD0),
-	PINMUX_SINGLE(TSN0_TX_CTL),
-	PINMUX_SINGLE(TSN0_AVTP_PPS0),
 	PINMUX_SINGLE(TSN0_RX_CTL),
 	PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
-	PINMUX_SINGLE(TSN0_AVTP_MATCH),
 	PINMUX_SINGLE(TSN0_LINK),
 	PINMUX_SINGLE(TSN0_PHY_INT),
-	PINMUX_SINGLE(TSN0_AVTP_PPS1),
-	PINMUX_SINGLE(TSN0_MDC),
 	PINMUX_SINGLE(TSN0_MDIO),
+	/* TSN0 with MDSEL4 */
+	PINMUX_IPSR_NOGM(0, TSN0_TD2,		SEL_TSN0_TD2_1),
+	PINMUX_IPSR_NOGM(0, TSN0_TD3,		SEL_TSN0_TD3_1),
+	PINMUX_IPSR_NOGM(0, TSN0_TD0,		SEL_TSN0_TD0_1),
+	PINMUX_IPSR_NOGM(0, TSN0_TD1,		SEL_TSN0_TD1_1),
+	PINMUX_IPSR_NOGM(0, TSN0_TXC,		SEL_TSN0_TXC_1),
+	PINMUX_IPSR_NOGM(0, TSN0_TX_CTL,	SEL_TSN0_TX_CTL_1),
+	PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS0,	SEL_TSN0_AVTP_PPS0_1),
+	PINMUX_IPSR_NOGM(0, TSN0_AVTP_MATCH,	SEL_TSN0_AVTP_MATCH_1),
+	PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1,	SEL_TSN0_AVTP_PPS1_1),
+	PINMUX_IPSR_NOGM(0, TSN0_MDC,		SEL_TSN0_MDC_1),
 
 	PINMUX_SINGLE(AVB2_RX_CTL),
 	PINMUX_SINGLE(AVB2_TX_CTL),