diff mbox series

drm/i915/display: Re-add check for low voltage sku for max dp source rate

Message ID 20220613102241.9236-1-Jason@zx2c4.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/display: Re-add check for low voltage sku for max dp source rate | expand

Commit Message

Jason A. Donenfeld June 13, 2022, 10:22 a.m. UTC
This reverts commit 73867c8709b569cdd7fda67f01dfe02c8d055521, which, on
an i7-11850H iGPU with a Thinkpad X1 Extreme Gen 4, attached to a LG
LP160UQ1-SPB1 embedded panel, causes wild flickering glitching
technicolor pyrotechnics on resumption from suspend. The display shows
strobing colors in an utter disaster explosion of pantone, as though
bombs were dropped on the leprechauns at the base of the rainbow.

Rebooting the machine fixes the issue, presumably because the display is
initialized by firmware rather than by i915. Otherwise, the GPU appears
to work fine.

Bisection traced it back to this commit, which makes sense given the
issues.

Fixes: 73867c8709b5 ("drm/i915/display: Remove check for low voltage sku for max dp source rate")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jani Saarinen <jani.saarinen@intel.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

Comments

Jani Nikula June 13, 2022, 11:05 a.m. UTC | #1
On Mon, 13 Jun 2022, "Jason A. Donenfeld" <Jason@zx2c4.com> wrote:
> This reverts commit 73867c8709b569cdd7fda67f01dfe02c8d055521, which, on
> an i7-11850H iGPU with a Thinkpad X1 Extreme Gen 4, attached to a LG
> LP160UQ1-SPB1 embedded panel, causes wild flickering glitching
> technicolor pyrotechnics on resumption from suspend. The display shows
> strobing colors in an utter disaster explosion of pantone, as though
> bombs were dropped on the leprechauns at the base of the rainbow.
>
> Rebooting the machine fixes the issue, presumably because the display is
> initialized by firmware rather than by i915. Otherwise, the GPU appears
> to work fine.
>
> Bisection traced it back to this commit, which makes sense given the
> issues.

Thanks for putting in the effort to bisect, and the patch.

As the commit message of the regressing commit suggests, the VBT (Video
BIOS Tables) should contain the info about max rates, filled in by the
OEM. Unfortunately, we were missing some of the checks,
e.g. 24b8b74eb2eb ("drm/i915: Parse max link rate from the eDP BDB
block") added to drm-intel-next just recently.

Unfortunately, gitlab is down today so I can't check if you already
tried drm-tip [1]; that might be helpful. Also, attaching
/sys/kernel/debug/dri/0/i915_vbt might be useful to see if the
limitation is there.

If your system works with the limitations from VBT, *and* the commits
adding that support are trivial to backport to v5.19, I'm inclined to do
that instead of the revert. But obviously the revert is the way to go if
that doesn't happen.

BR,
Jani.


[1] drm-tip branch of https://cgit.freedesktop.org/drm/drm-tip


>
> Fixes: 73867c8709b5 ("drm/i915/display: Remove check for low voltage sku for max dp source rate")
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Jani Saarinen <jani.saarinen@intel.com>
> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++++++++++++++++++++---
>  1 file changed, 29 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index e4a79c11fd25..ff67899522cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -388,13 +388,23 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp)
>  	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
>  }
>  
> +static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
> +{
> +	u32 voltage;
> +
> +	voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
> +
> +	return voltage == VOLTAGE_INFO_0_85V;
> +}
> +
>  static int icl_max_source_rate(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>  	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
>  
> -	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
> +	if (intel_phy_is_combo(dev_priv, phy) &&
> +	    (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
>  		return 540000;
>  
>  	return 810000;
> @@ -402,7 +412,23 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
>  
>  static int ehl_max_source_rate(struct intel_dp *intel_dp)
>  {
> -	if (intel_dp_is_edp(intel_dp))
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
> +
> +	if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
> +		return 540000;
> +
> +	return 810000;
> +}
> +
> +static int dg1_max_source_rate(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> +
> +	if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
>  		return 540000;
>  
>  	return 810000;
> @@ -445,7 +471,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  			max_rate = dg2_max_source_rate(intel_dp);
>  		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
>  			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> -			max_rate = 810000;
> +			max_rate = dg1_max_source_rate(intel_dp);
>  		else if (IS_JSL_EHL(dev_priv))
>  			max_rate = ehl_max_source_rate(intel_dp);
>  		else
Jason A. Donenfeld June 13, 2022, 12:05 p.m. UTC | #2
Hi Jani,

On Mon, Jun 13, 2022 at 02:05:17PM +0300, Jani Nikula wrote:
> On Mon, 13 Jun 2022, "Jason A. Donenfeld" <Jason@zx2c4.com> wrote:
> > This reverts commit 73867c8709b569cdd7fda67f01dfe02c8d055521, which, on
> > an i7-11850H iGPU with a Thinkpad X1 Extreme Gen 4, attached to a LG
> > LP160UQ1-SPB1 embedded panel, causes wild flickering glitching
> > technicolor pyrotechnics on resumption from suspend. The display shows
> > strobing colors in an utter disaster explosion of pantone, as though
> > bombs were dropped on the leprechauns at the base of the rainbow.
> >
> > Rebooting the machine fixes the issue, presumably because the display is
> > initialized by firmware rather than by i915. Otherwise, the GPU appears
> > to work fine.
> >
> > Bisection traced it back to this commit, which makes sense given the
> > issues.
> 
> Thanks for putting in the effort to bisect, and the patch.
> 
> As the commit message of the regressing commit suggests, the VBT (Video
> BIOS Tables) should contain the info about max rates, filled in by the
> OEM. Unfortunately, we were missing some of the checks,
> e.g. 24b8b74eb2eb ("drm/i915: Parse max link rate from the eDP BDB
> block") added to drm-intel-next just recently.
> 
> Unfortunately, gitlab is down today so I can't check if you already
> tried drm-tip [1]; that might be helpful. Also, attaching
> /sys/kernel/debug/dri/0/i915_vbt might be useful to see if the
> limitation is there.
> 
> If your system works with the limitations from VBT, *and* the commits
> adding that support are trivial to backport to v5.19, I'm inclined to do
> that instead of the revert. But obviously the revert is the way to go if
> that doesn't happen.

I checked with drm-tip last week when I filed the bug, and I just
remerged the latest today, just in case there was anything new, and
alas, the problem still occurs.

Jason
Jason A. Donenfeld June 20, 2022, 11:26 a.m. UTC | #3
Hi Jani,

Do you plan to merge this revert?

Thanks,
Jason
Jani Nikula June 20, 2022, 4:10 p.m. UTC | #4
On Mon, 20 Jun 2022, "Jason A. Donenfeld" <Jason@zx2c4.com> wrote:
> Hi Jani,
>
> Do you plan to merge this revert?

Yes, I've done that now, thanks for the bisection and the patch.

Ankit, Imre, we need to figure out what to do with [1] now.

BR,
Jani.


[1] https://gitlab.freedesktop.org/drm/intel/-/issues/5272
Jason A. Donenfeld June 20, 2022, 4:16 p.m. UTC | #5
Hi Jani,

On Mon, Jun 20, 2022 at 07:10:30PM +0300, Jani Nikula wrote:
> On Mon, 20 Jun 2022, "Jason A. Donenfeld" <Jason@zx2c4.com> wrote:
> > Hi Jani,
> >
> > Do you plan to merge this revert?
> 
> Yes, I've done that now, thanks for the bisection and the patch.

Thanks!

I see that this went into `drm-intel-next`, but shouldn't it go into
`drm-intel-fixes`, so that it makes it into 5.19-rc4?

Jason
Jani Nikula June 20, 2022, 4:26 p.m. UTC | #6
On Mon, 20 Jun 2022, "Jason A. Donenfeld" <Jason@zx2c4.com> wrote:
> Hi Jani,
>
> On Mon, Jun 20, 2022 at 07:10:30PM +0300, Jani Nikula wrote:
>> On Mon, 20 Jun 2022, "Jason A. Donenfeld" <Jason@zx2c4.com> wrote:
>> > Hi Jani,
>> >
>> > Do you plan to merge this revert?
>> 
>> Yes, I've done that now, thanks for the bisection and the patch.
>
> Thanks!
>
> I see that this went into `drm-intel-next`, but shouldn't it go into
> `drm-intel-fixes`, so that it makes it into 5.19-rc4?

All of our commits go to drm-intel-next first. I'll pick it up for fixes
later.

BR,
Jani.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e4a79c11fd25..ff67899522cf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -388,13 +388,23 @@  static int dg2_max_source_rate(struct intel_dp *intel_dp)
 	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 }
 
+static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
+{
+	u32 voltage;
+
+	voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
+
+	return voltage == VOLTAGE_INFO_0_85V;
+}
+
 static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
-	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
+	if (intel_phy_is_combo(dev_priv, phy) &&
+	    (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
 		return 540000;
 
 	return 810000;
@@ -402,7 +412,23 @@  static int icl_max_source_rate(struct intel_dp *intel_dp)
 
 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 {
-	if (intel_dp_is_edp(intel_dp))
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
+
+	if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
+		return 540000;
+
+	return 810000;
+}
+
+static int dg1_max_source_rate(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+	if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
 		return 540000;
 
 	return 810000;
@@ -445,7 +471,7 @@  intel_dp_set_source_rates(struct intel_dp *intel_dp)
 			max_rate = dg2_max_source_rate(intel_dp);
 		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
-			max_rate = 810000;
+			max_rate = dg1_max_source_rate(intel_dp);
 		else if (IS_JSL_EHL(dev_priv))
 			max_rate = ehl_max_source_rate(intel_dp);
 		else