| Message ID | 20220616141950.23374-3-Jonathan.Cameron@huawei.com |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | arm/virt: CXL support via pxb_cxl | expand |
On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: > > Add a single complex case for aarch64 virt machine. > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > tests/qtest/cxl-test.c | 48 +++++++++++++++++++++++++++++++++-------- > tests/qtest/meson.build | 1 + > 2 files changed, 40 insertions(+), 9 deletions(-) > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: > > Add a single complex case for aarch64 virt machine. > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > tests/qtest/cxl-test.c | 48 +++++++++++++++++++++++++++++++++-------- > tests/qtest/meson.build | 1 + > 2 files changed, 40 insertions(+), 9 deletions(-) > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > index 2133e973f4..1015d0e7c2 100644 > --- a/tests/qtest/cxl-test.c > +++ b/tests/qtest/cxl-test.c > @@ -17,6 +17,11 @@ > "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > > +#define QEMU_VIRT_2PXB_CMD "-machine virt,cxl=on " \ > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > + If CXL requires booting via UEFI, what does this test case do? It doesn't seem to be passing in a BIOS image. thanks -- PMM
On Fri, 24 Jun 2022 17:12:25 +0100 Peter Maydell <peter.maydell@linaro.org> wrote: > On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron > <Jonathan.Cameron@huawei.com> wrote: > > > > Add a single complex case for aarch64 virt machine. > > > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > --- > > tests/qtest/cxl-test.c | 48 +++++++++++++++++++++++++++++++++-------- > > tests/qtest/meson.build | 1 + > > 2 files changed, 40 insertions(+), 9 deletions(-) > > > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > > index 2133e973f4..1015d0e7c2 100644 > > --- a/tests/qtest/cxl-test.c > > +++ b/tests/qtest/cxl-test.c > > @@ -17,6 +17,11 @@ > > "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > > "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > > > > +#define QEMU_VIRT_2PXB_CMD "-machine virt,cxl=on " \ > > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > > + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > > + > > If CXL requires booting via UEFI, what does this test case do? > It doesn't seem to be passing in a BIOS image. Not a lot beyond checking device creation is valid etc and the machine boots. There is a bios tables test that checks we pass the right tables to the BIOS image. I didn't duplicate that for ARM on the basis it's more or less identical, but perhaps that is worth adding. To do any useful functional testing will require a mass of complex OS handling after booting. That testing is definitely something I'd like to add, but the userspace tooling isn't all in place yet. Final kernel series that's needed to get to the point where you can use the non volatile memory had a new version posted yesterday. Jonathan > > thanks > -- PMM
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index 2133e973f4..1015d0e7c2 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -17,6 +17,11 @@ "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " +#define QEMU_VIRT_2PXB_CMD "-machine virt,cxl=on " \ + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " + #define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " /* Dual ports on first pxb */ @@ -134,18 +139,43 @@ static void cxl_2pxb_4rp_4t3d(void) qtest_end(); } +static void cxl_virt_2pxb_4rp_4t3d(void) +{ + g_autoptr(GString) cmdline = g_string_new(NULL); + char template[] = "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs = mkdtemp(template); + + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); +} + int main(int argc, char **argv) { + const char *arch = qtest_get_arch(); + g_test_init(&argc, &argv, NULL); - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); - qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); - qtest_add_func("/pci/cxl/rp", cxl_root_port); - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); - qtest_add_func("/pci/cxl/type3_device", cxl_t3d); - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d); + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); + qtest_add_func("/pci/cxl/rp", cxl_root_port); + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); + qtest_add_func("/pci/cxl/type3_device", cxl_t3d); + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", + cxl_2pxb_4rp_4t3d); + } else if (strcmp(arch, "aarch64") == 0) { + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", + cxl_virt_2pxb_4rp_4t3d); + } + return g_test_run(); } diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 31287a9173..0fa93da13a 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -215,6 +215,7 @@ qtests_aarch64 = \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ + qtests_cxl + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test',
Add a single complex case for aarch64 virt machine. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- tests/qtest/cxl-test.c | 48 +++++++++++++++++++++++++++++++++-------- tests/qtest/meson.build | 1 + 2 files changed, 40 insertions(+), 9 deletions(-)