| Message ID | 20220624180311.3007-2-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add PLIC support for Renesas RZ/Five SoC | expand |
On 24/06/2022 20:03, Lad Prabhakar wrote: > Document Renesas RZ/Five (R9A07G043) SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > RFC->v1: > * Fixed Review comments pointed by Geert and Rob > --- > .../sifive,plic-1.0.0.yaml | 40 +++++++++++++++++-- > 1 file changed, 36 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index 27092c6a86c4..5eebe0b01b4d 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -28,7 +28,10 @@ description: > > While the PLIC supports both edge-triggered and level-triggered interrupts, > interrupt handlers are oblivious to this distinction and therefore it is not > - specified in the PLIC device-tree binding. > + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's), > + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need > + to specify the interrupt type as the flow for EDGE interrupts is different > + compared to LEVEL interrupts. > > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that > @@ -57,6 +60,7 @@ properties: > - enum: > - allwinner,sun20i-d1-plic > - const: thead,c900-plic > + - const: renesas,r9a07g043-plic > > reg: > maxItems: 1 > @@ -64,8 +68,7 @@ properties: > '#address-cells': > const: 0 > > - '#interrupt-cells': > - const: 1 > + '#interrupt-cells': true > > interrupt-controller: true > > @@ -91,7 +94,36 @@ required: > - interrupts-extended > - riscv,ndev > > -additionalProperties: false > +if: Make it inside allOf. Avoids further indentation change on next variant. > + properties: > + compatible: > + contains: > + const: renesas,r9a07g043-plic > +then: > + properties: > + clocks: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + '#interrupt-cells': > + const: 2 > + > + required: > + - clocks > + - resets > + - power-domains > + > +else: > + properties: > + '#interrupt-cells': > + const: 1 > + > +unevaluatedProperties: false This does not look correct, why changing additional->unevaluated here? Best regards, Krzysztof
Hi Krzysztof, Thank you for the review. On Sat, Jun 25, 2022 at 9:01 PM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 24/06/2022 20:03, Lad Prabhakar wrote: > > Document Renesas RZ/Five (R9A07G043) SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > RFC->v1: > > * Fixed Review comments pointed by Geert and Rob > > --- > > .../sifive,plic-1.0.0.yaml | 40 +++++++++++++++++-- > > 1 file changed, 36 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > index 27092c6a86c4..5eebe0b01b4d 100644 > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > @@ -28,7 +28,10 @@ description: > > > > While the PLIC supports both edge-triggered and level-triggered interrupts, > > interrupt handlers are oblivious to this distinction and therefore it is not > > - specified in the PLIC device-tree binding. > > + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's), > > + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need > > + to specify the interrupt type as the flow for EDGE interrupts is different > > + compared to LEVEL interrupts. > > > > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that > > @@ -57,6 +60,7 @@ properties: > > - enum: > > - allwinner,sun20i-d1-plic > > - const: thead,c900-plic > > + - const: renesas,r9a07g043-plic > > > > reg: > > maxItems: 1 > > @@ -64,8 +68,7 @@ properties: > > '#address-cells': > > const: 0 > > > > - '#interrupt-cells': > > - const: 1 > > + '#interrupt-cells': true > > > > interrupt-controller: true > > > > @@ -91,7 +94,36 @@ required: > > - interrupts-extended > > - riscv,ndev > > > > -additionalProperties: false > > +if: > > Make it inside allOf. Avoids further indentation change on next variant. > Agreed. > > + properties: > > + compatible: > > + contains: > > + const: renesas,r9a07g043-plic > > +then: > > + properties: > > + clocks: > > + maxItems: 1 > > + > > + resets: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + '#interrupt-cells': > > + const: 2 > > + > > + required: > > + - clocks > > + - resets > > + - power-domains > > + > > +else: > > + properties: > > + '#interrupt-cells': > > + const: 1 > > + > > +unevaluatedProperties: false > > > This does not look correct, why changing additional->unevaluated here? > Agreed will drop this. Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 27092c6a86c4..5eebe0b01b4d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -28,7 +28,10 @@ description: While the PLIC supports both edge-triggered and level-triggered interrupts, interrupt handlers are oblivious to this distinction and therefore it is not - specified in the PLIC device-tree binding. + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's), + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need + to specify the interrupt type as the flow for EDGE interrupts is different + compared to LEVEL interrupts. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that @@ -57,6 +60,7 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - const: renesas,r9a07g043-plic reg: maxItems: 1 @@ -64,8 +68,7 @@ properties: '#address-cells': const: 0 - '#interrupt-cells': - const: 1 + '#interrupt-cells': true interrupt-controller: true @@ -91,7 +94,36 @@ required: - interrupts-extended - riscv,ndev -additionalProperties: false +if: + properties: + compatible: + contains: + const: renesas,r9a07g043-plic +then: + properties: + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#interrupt-cells': + const: 2 + + required: + - clocks + - resets + - power-domains + +else: + properties: + '#interrupt-cells': + const: 1 + +unevaluatedProperties: false examples: - |
Document Renesas RZ/Five (R9A07G043) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- RFC->v1: * Fixed Review comments pointed by Geert and Rob --- .../sifive,plic-1.0.0.yaml | 40 +++++++++++++++++-- 1 file changed, 36 insertions(+), 4 deletions(-)