| Message ID | 20220627194003.2395484-7-mail@conchuod.ie (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Canaan devicetree fixes | expand |
On Mon, Jun 27, 2022 at 08:39:54PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The Canaan k210 apparently has a Sysnopsys Designware timer but > according to the documentation & devicetree it has 2 interrupts rather > than the standard one. Add a custom compatible that supports the 2 > interrupt configuration and falls back to the standard binding (which > is currently the one in use in the devicetree entry). > > Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58 Firstly, it's page 51 in the framework of the document pages enumeration. Judging by the comment in the document above and what the HW reference manual says regarding the IRQ signals, what you really have on K210 is the DW APB Timer IP-cores each configured with two embedded timers. It's done by the IP-core synthesize parameter NUM_TIMERS={1..8}, which in your case equals to 2. A similar situation is on our SoC and, for instance, here: arch/arm/boot/dts/berlin2q.dtsi arch/arm/boot/dts/berlin2.dtsi arch/arm/boot/dts/berlin2cd.dtsi (Though the Berlin2 APB Timer have been configured with 8 timers.) So the correct modification would be: 1. Split up the nodes into two ones with one IRQ per each node. 2. Make sure I was right by testing the new dts out. 3. Update the DT-node only and leave the DT-bindings as is. -Sergey > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++---- > 1 file changed, 22 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml > index d33c9205a909..9a76acc7a66f 100644 > --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml > +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml > @@ -12,6 +12,9 @@ maintainers: > properties: > compatible: > oneOf: > + - items: > + - const: canaan,k210-apb-timer > + - const: snps,dw-apb-timer > - const: snps,dw-apb-timer > - enum: > - snps,dw-apb-timer-sp > @@ -21,9 +24,6 @@ properties: > reg: > maxItems: 1 > > - interrupts: > - maxItems: 1 > - > resets: > maxItems: 1 > > @@ -41,7 +41,23 @@ properties: > > clock-frequency: true > > -additionalProperties: false > +unevaluatedProperties: false > + > +if: > + properties: > + compatible: > + contains: > + const: canaan,k210-apb-timer > + > +then: > + properties: > + interrupts: > + maxItems: 2 > + > +else: > + properties: > + interrupts: > + maxItems: 1 > > required: > - compatible > @@ -60,8 +76,8 @@ oneOf: > examples: > - | > timer@ffe00000 { > - compatible = "snps,dw-apb-timer"; > - interrupts = <0 170 4>; > + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer"; > + interrupts = <0 170 4>, <0 170 4>; > reg = <0xffe00000 0x1000>; > clocks = <&timer_clk>, <&timer_pclk>; > clock-names = "timer", "pclk"; > -- > 2.36.1 >
On 27/06/2022 22:13, Serge Semin wrote: > On Mon, Jun 27, 2022 at 08:39:54PM +0100, Conor Dooley wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> The Canaan k210 apparently has a Sysnopsys Designware timer but >> according to the documentation & devicetree it has 2 interrupts rather >> than the standard one. Add a custom compatible that supports the 2 >> interrupt configuration and falls back to the standard binding (which >> is currently the one in use in the devicetree entry). >> > >> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58 > > Firstly, it's page 51 in the framework of the document pages > enumeration. Ah yes, sorry about that. > > Judging by the comment in the document above and what the HW reference > manual says regarding the IRQ signals, what you really have on K210 is > the DW APB Timer IP-cores each configured with two embedded timers. > It's done by the IP-core synthesize parameter NUM_TIMERS={1..8}, which > in your case equals to 2. A similar situation is on our SoC and, for > instance, here: > > arch/arm/boot/dts/berlin2q.dtsi > arch/arm/boot/dts/berlin2.dtsi > arch/arm/boot/dts/berlin2cd.dtsi > (Though the Berlin2 APB Timer have been configured with 8 timers.) > > So the correct modification would be: > 1. Split up the nodes into two ones with one IRQ per each node. > 2. Make sure I was right by testing the new dts out. > 3. Update the DT-node only and leave the DT-bindings as is. Hmm, sounds good. Will give that a whirl tomorrow. Thanks for the info/suggestions Sergey.
diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml index d33c9205a909..9a76acc7a66f 100644 --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml @@ -12,6 +12,9 @@ maintainers: properties: compatible: oneOf: + - items: + - const: canaan,k210-apb-timer + - const: snps,dw-apb-timer - const: snps,dw-apb-timer - enum: - snps,dw-apb-timer-sp @@ -21,9 +24,6 @@ properties: reg: maxItems: 1 - interrupts: - maxItems: 1 - resets: maxItems: 1 @@ -41,7 +41,23 @@ properties: clock-frequency: true -additionalProperties: false +unevaluatedProperties: false + +if: + properties: + compatible: + contains: + const: canaan,k210-apb-timer + +then: + properties: + interrupts: + maxItems: 2 + +else: + properties: + interrupts: + maxItems: 1 required: - compatible @@ -60,8 +76,8 @@ oneOf: examples: - | timer@ffe00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 170 4>; + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer"; + interrupts = <0 170 4>, <0 170 4>; reg = <0xffe00000 0x1000>; clocks = <&timer_clk>, <&timer_pclk>; clock-names = "timer", "pclk";