| Message ID | 20220629121358.19458-4-allen-kh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Complete driver nodes for MT8192 SoC | expand |
On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote: > Add display nodes and gce info for mt8192 SoC. > > GCE (Global Command Engine) properties to the display nodes in order to > enable the usage of the CMDQ (Command Queue), which is required for > operating the display. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136 +++++++++++++++++++++++ > 1 file changed, 136 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index a07edc82d403..26d01544b4ea 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi [..] > > + mutex: mutex@14001000 { > + compatible = "mediatek,mt8192-disp-mutex"; > + reg = <0 0x14001000 0 0x1000>; > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, > + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; This node is missing power-domains. > + }; > + [..] > + rdma0: rdma@14007000 { > + compatible = "mediatek,mt8192-disp-rdma"; dtbs_check is complaining that there isn't a "mediatek,mt8183-disp-rdma" fallback compatible here. But given that the rdma driver matches directly to the mt8192 compatible, I think the node here is fine, and the binding is the one that should be updated. > + reg = <0 0x14007000 0 0x1000>; > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > + mediatek,larb = <&larb0>; mediatek,larb is no longer used, so drop it. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Thanks, Nícolas
Hi Nícolas, On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote: > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote: > > Add display nodes and gce info for mt8192 SoC. > > > > GCE (Global Command Engine) properties to the display nodes in > > order to > > enable the usage of the CMDQ (Command Queue), which is required for > > operating the display. > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136 > > +++++++++++++++++++++++ > > 1 file changed, 136 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index a07edc82d403..26d01544b4ea 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > [..] > > > > + mutex: mutex@14001000 { > > + compatible = "mediatek,mt8192-disp-mutex"; > > + reg = <0 0x14001000 0 0x1000>; > > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > > + mediatek,gce-events = > > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, > > + <CMDQ_EVENT_DISP_STREAM_D > > ONE_ENG_EVENT_1>; > > This node is missing power-domains. > > > + }; > > > > [..] > > + rdma0: rdma@14007000 { > > + compatible = "mediatek,mt8192-disp-rdma"; > > dtbs_check is complaining that there isn't a "mediatek,mt8183-disp- > rdma" > fallback compatible here. But given that the rdma driver matches > directly to the > mt8192 compatible, I think the node here is fine, and the binding is > the one > that should be updated. > I have checked the binding and driver again. I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove mt8192 compatible and data in mtk_disp_rdma.c because they are the same with mt8183. Do you think it is okay? Thanks, Allen > > + reg = <0 0x14007000 0 0x1000>; > > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > > + mediatek,larb = <&larb0>; > > mediatek,larb is no longer used, so drop it. > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > > Thanks, > Nícolas
On Thu, Jun 30, 2022 at 05:41:31PM +0800, allen-kh.cheng wrote: > Hi Nícolas, > > On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote: > > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote: > > > Add display nodes and gce info for mt8192 SoC. > > > > > > GCE (Global Command Engine) properties to the display nodes in > > > order to > > > enable the usage of the CMDQ (Command Queue), which is required for > > > operating the display. > > > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > > Reviewed-by: AngeloGioacchino Del Regno < > > > angelogioacchino.delregno@collabora.com> > > > --- > > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136 > > > +++++++++++++++++++++++ > > > 1 file changed, 136 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > index a07edc82d403..26d01544b4ea 100644 > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi [..] > > > + rdma0: rdma@14007000 { > > > + compatible = "mediatek,mt8192-disp-rdma"; > > > > dtbs_check is complaining that there isn't a "mediatek,mt8183-disp- > > rdma" > > fallback compatible here. But given that the rdma driver matches > > directly to the > > mt8192 compatible, I think the node here is fine, and the binding is > > the one > > that should be updated. > > > > I have checked the binding and driver again. > > I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove mt8192 > compatible and data in mtk_disp_rdma.c because they are the same with > mt8183. > > Do you think it is okay? Sure, that sounds good to me as well. Thanks, Nícolas
On Thu, Jun 30, 2022 at 9:42 PM Nícolas F. R. A. Prado <nfraprado@collabora.com> wrote: > > On Thu, Jun 30, 2022 at 05:41:31PM +0800, allen-kh.cheng wrote: > > Hi Nícolas, > > > > On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote: > > > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote: > > > > Add display nodes and gce info for mt8192 SoC. > > > > > > > > GCE (Global Command Engine) properties to the display nodes in > > > > order to > > > > enable the usage of the CMDQ (Command Queue), which is required for > > > > operating the display. > > > > > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > > > Reviewed-by: AngeloGioacchino Del Regno < > > > > angelogioacchino.delregno@collabora.com> > > > > --- > > > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136 > > > > +++++++++++++++++++++++ > > > > 1 file changed, 136 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > > index a07edc82d403..26d01544b4ea 100644 > > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > [..] > > > > + rdma0: rdma@14007000 { > > > > + compatible = "mediatek,mt8192-disp-rdma"; > > > > > > dtbs_check is complaining that there isn't a "mediatek,mt8183-disp- > > > rdma" > > > fallback compatible here. But given that the rdma driver matches > > > directly to the > > > mt8192 compatible, I think the node here is fine, and the binding is > > > the one > > > that should be updated. > > > > > > > I have checked the binding and driver again. > > > > I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove mt8192 > > compatible and data in mtk_disp_rdma.c because they are the same with > > mt8183. > > > > Do you think it is okay? > > Sure, that sounds good to me as well. That's backwards. MT8192 was released well before MT8186. The latter hasn't even hit the market yet. Please use "mediatek,mt8183-disp-rdma" as fallback. And you need to keep "mediatek,mt8192-disp-rdma" as the most specific compatible string, because we want SoC specific compatible strings. For the driver, there isn't any difference between mt8183 and mt8192 for the rdma part, so we might as well just remove the mt8192 compatible from the driver. Regards ChenYu
Hi Chen-Yu, On Fri, 2022-07-01 at 13:25 +0800, Chen-Yu Tsai wrote: > On Thu, Jun 30, 2022 at 9:42 PM Nícolas F. R. A. Prado > <nfraprado@collabora.com> wrote: > > > > On Thu, Jun 30, 2022 at 05:41:31PM +0800, allen-kh.cheng wrote: > > > Hi Nícolas, > > > > > > On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote: > > > > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote: > > > > > Add display nodes and gce info for mt8192 SoC. > > > > > > > > > > GCE (Global Command Engine) properties to the display nodes > > > > > in > > > > > order to > > > > > enable the usage of the CMDQ (Command Queue), which is > > > > > required for > > > > > operating the display. > > > > > > > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > > > > Reviewed-by: AngeloGioacchino Del Regno < > > > > > angelogioacchino.delregno@collabora.com> > > > > > --- > > > > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136 > > > > > +++++++++++++++++++++++ > > > > > 1 file changed, 136 insertions(+) > > > > > > > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > > > index a07edc82d403..26d01544b4ea 100644 > > > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > > > [..] > > > > > + rdma0: rdma@14007000 { > > > > > + compatible = "mediatek,mt8192-disp-rdma"; > > > > > > > > dtbs_check is complaining that there isn't a "mediatek,mt8183- > > > > disp- > > > > rdma" > > > > fallback compatible here. But given that the rdma driver > > > > matches > > > > directly to the > > > > mt8192 compatible, I think the node here is fine, and the > > > > binding is > > > > the one > > > > that should be updated. > > > > > > > > > > I have checked the binding and driver again. > > > > > > I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove > > > mt8192 > > > compatible and data in mtk_disp_rdma.c because they are the same > > > with > > > mt8183. > > > > > > Do you think it is okay? > > > > Sure, that sounds good to me as well. > > That's backwards. MT8192 was released well before MT8186. The latter > hasn't > even hit the market yet. > > Please use "mediatek,mt8183-disp-rdma" as fallback. And you need to > keep > "mediatek,mt8192-disp-rdma" as the most specific compatible string, > because > we want SoC specific compatible strings. > > For the driver, there isn't any difference between mt8183 and mt8192 > for > the rdma part, so we might as well just remove the mt8192 compatible > from > the driver. > > > Regards > ChenYu Yes, I agree with you. it appears that for some reasons I made a typo in my repy. I will use "mediatek,mt8183-disp-rdma" as fallback in next version. Thanks, Allen
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a07edc82d403..26d01544b4ea 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/clock/mt8192-clk.h> +#include <dt-bindings/gce/mt8192-gce.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/memory/mt8192-larb-port.h> @@ -553,6 +554,15 @@ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; }; + gce: mailbox@10228000 { + compatible = "mediatek,mt8192-gce"; + reg = <0 0x10228000 0 0x4000>; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; @@ -1186,9 +1196,21 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8192-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; #clock-cells = <1>; }; + mutex: mutex@14001000 { + compatible = "mediatek,mt8192-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; + }; + smi_common: smi@14002000 { compatible = "mediatek,mt8192-smi-common"; reg = <0 0x14002000 0 0x1000>; @@ -1220,6 +1242,120 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; + ovl0: ovl@14005000 { + compatible = "mediatek,mt8192-disp-ovl"; + reg = <0 0x14005000 0 0x1000>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + }; + + ovl_2l0: ovl@14006000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14006000 0 0x1000>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + }; + + rdma0: rdma@14007000 { + compatible = "mediatek,mt8192-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; + mediatek,larb = <&larb0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + }; + + color0: color@14009000 { + compatible = "mediatek,mt8192-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + ccorr0: ccorr@1400a000 { + compatible = "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + aal0: aal@1400b000 { + compatible = "mediatek,mt8192-disp-aal", + "mediatek,mt8183-disp-aal"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + gamma0: gamma@1400c000 { + compatible = "mediatek,mt8192-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + postmask0: postmask@1400d000 { + compatible = "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + }; + + dither0: dither@1400e000 { + compatible = "mediatek,mt8192-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + ovl_2l2: ovl@14014000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; + }; + + rdma4: rdma@14015000 { + compatible = "mediatek,mt8192-disp-rdma"; + reg = <0 0x14015000 0 0x1000>; + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA4>; + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; + mediatek,rdma-fifo-size = <2048>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + }; + dpi0: dpi@14016000 { compatible = "mediatek,mt8192-dpi"; reg = <0 0x14016000 0 0x1000>;