| Message ID | 20220629120700.620108-1-jarkko.nikula@linux.intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 3190d4be3764fd847d57e26197158940e89272ae |
| Headers | show |
| Series | spi: pxa2xx: Add support for Intel Meteor Lake PCH-P | expand |
On Wed, Jun 29, 2022 at 2:09 PM Jarkko Nikula <jarkko.nikula@linux.intel.com> wrote: > > Add support for LPSS SPI on Intel Meteor Lake PCH-P. It has three > controllers each having two chip selects. > > This squashes a fix from Ap, Kamal <kamal.ap@intel.com> fixing incorrect > PCI ID of 3rd controller. With PCH removed from the commit message (including subject) Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> > Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> > --- > drivers/spi/spi-pxa2xx.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c > index edb42d08857d..838d12e65144 100644 > --- a/drivers/spi/spi-pxa2xx.c > +++ b/drivers/spi/spi-pxa2xx.c > @@ -1404,6 +1404,10 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { > { PCI_VDEVICE(INTEL, 0x7aab), LPSS_CNL_SSP }, > { PCI_VDEVICE(INTEL, 0x7af9), LPSS_CNL_SSP }, > { PCI_VDEVICE(INTEL, 0x7afb), LPSS_CNL_SSP }, > + /* MTL-P */ > + { PCI_VDEVICE(INTEL, 0x7e27), LPSS_CNL_SSP }, > + { PCI_VDEVICE(INTEL, 0x7e30), LPSS_CNL_SSP }, > + { PCI_VDEVICE(INTEL, 0x7e46), LPSS_CNL_SSP }, > /* CNL-LP */ > { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, > { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, > -- > 2.35.1 >
On 6/29/22 18:35, Andy Shevchenko wrote: > On Wed, Jun 29, 2022 at 2:09 PM Jarkko Nikula > <jarkko.nikula@linux.intel.com> wrote: >> >> Add support for LPSS SPI on Intel Meteor Lake PCH-P. It has three >> controllers each having two chip selects. >> >> This squashes a fix from Ap, Kamal <kamal.ap@intel.com> fixing incorrect >> PCI ID of 3rd controller. > > With PCH removed from the commit message (including subject) > Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> > Hmm, right. Thanks Andy, Meteor Lake -P seems to integrate PCH die functionality into a SoC. Jarkko
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index edb42d08857d..838d12e65144 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -1404,6 +1404,10 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { { PCI_VDEVICE(INTEL, 0x7aab), LPSS_CNL_SSP }, { PCI_VDEVICE(INTEL, 0x7af9), LPSS_CNL_SSP }, { PCI_VDEVICE(INTEL, 0x7afb), LPSS_CNL_SSP }, + /* MTL-P */ + { PCI_VDEVICE(INTEL, 0x7e27), LPSS_CNL_SSP }, + { PCI_VDEVICE(INTEL, 0x7e30), LPSS_CNL_SSP }, + { PCI_VDEVICE(INTEL, 0x7e46), LPSS_CNL_SSP }, /* CNL-LP */ { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
Add support for LPSS SPI on Intel Meteor Lake PCH-P. It has three controllers each having two chip selects. This squashes a fix from Ap, Kamal <kamal.ap@intel.com> fixing incorrect PCI ID of 3rd controller. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> --- drivers/spi/spi-pxa2xx.c | 4 ++++ 1 file changed, 4 insertions(+)