Message ID | 20220629184343.3438856-9-mail@conchuod.ie (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Canaan devicetree fixes | expand |
On Wed, Jun 29, 2022 at 07:43:37PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The timers on the k210 have non standard interrupt configurations, > which leads to dtbs_check warnings: > > k210_generic.dtb: timer@502d0000: interrupts: [[14], [15]] is too long > From schema: Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml > > Split the timer nodes in two, so that the second timer in the IP block > can actually be accessed & in the process solve the dtbs_check warning. Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Just to note. IMO the DW APB Timer driver has been incorrectly designed in the first place. The dts-node is supposed to describe the whole IP-core timers set as the original Canaan k210 DT-file expected, since there are common CSRs in the registers range, which currently get to be unreachable. But since the DT-bindings has already been defined that way in the framework of DW APB Timer driver alas there is nothing we can do to fix it. -Sergey > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/boot/dts/canaan/k210.dtsi | 46 +++++++++++++++++++++++----- > 1 file changed, 38 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi > index cd4eae82d8b2..72f70128d751 100644 > --- a/arch/riscv/boot/dts/canaan/k210.dtsi > +++ b/arch/riscv/boot/dts/canaan/k210.dtsi > @@ -319,28 +319,58 @@ fpioa: pinmux@502b0000 { > > timer0: timer@502d0000 { > compatible = "snps,dw-apb-timer"; > - reg = <0x502D0000 0x100>; > - interrupts = <14>, <15>; > + reg = <0x502D0000 0x14>; > + interrupts = <14>; > clocks = <&sysclk K210_CLK_TIMER0>, > <&sysclk K210_CLK_APB0>; > clock-names = "timer", "pclk"; > resets = <&sysrst K210_RST_TIMER0>; > }; > > - timer1: timer@502e0000 { > + timer1: timer@502d0014 { > compatible = "snps,dw-apb-timer"; > - reg = <0x502E0000 0x100>; > - interrupts = <16>, <17>; > + reg = <0x502D0014 0x14>; > + interrupts = <15>; > + clocks = <&sysclk K210_CLK_TIMER0>, > + <&sysclk K210_CLK_APB0>; > + clock-names = "timer", "pclk"; > + resets = <&sysrst K210_RST_TIMER0>; > + }; > + > + timer2: timer@502e0000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x502E0000 0x14>; > + interrupts = <16>; > clocks = <&sysclk K210_CLK_TIMER1>, > <&sysclk K210_CLK_APB0>; > clock-names = "timer", "pclk"; > resets = <&sysrst K210_RST_TIMER1>; > }; > > - timer2: timer@502f0000 { > + timer3: timer@502e0014 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x502E0014 0x114>; > + interrupts = <17>; > + clocks = <&sysclk K210_CLK_TIMER1>, > + <&sysclk K210_CLK_APB0>; > + clock-names = "timer", "pclk"; > + resets = <&sysrst K210_RST_TIMER1>; > + }; > + > + timer4: timer@502f0000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x502F0000 0x14>; > + interrupts = <18>; > + clocks = <&sysclk K210_CLK_TIMER2>, > + <&sysclk K210_CLK_APB0>; > + clock-names = "timer", "pclk"; > + resets = <&sysrst K210_RST_TIMER2>; > + }; > + > + timer5: timer@502f0014 { > compatible = "snps,dw-apb-timer"; > - reg = <0x502F0000 0x100>; > - interrupts = <18>, <19>; > + reg = <0x502F0014 0x14>; > + interrupts = <19>; > clocks = <&sysclk K210_CLK_TIMER2>, > <&sysclk K210_CLK_APB0>; > clock-names = "timer", "pclk"; > -- > 2.36.1 >
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index cd4eae82d8b2..72f70128d751 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -319,28 +319,58 @@ fpioa: pinmux@502b0000 { timer0: timer@502d0000 { compatible = "snps,dw-apb-timer"; - reg = <0x502D0000 0x100>; - interrupts = <14>, <15>; + reg = <0x502D0000 0x14>; + interrupts = <14>; clocks = <&sysclk K210_CLK_TIMER0>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER0>; }; - timer1: timer@502e0000 { + timer1: timer@502d0014 { compatible = "snps,dw-apb-timer"; - reg = <0x502E0000 0x100>; - interrupts = <16>, <17>; + reg = <0x502D0014 0x14>; + interrupts = <15>; + clocks = <&sysclk K210_CLK_TIMER0>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER0>; + }; + + timer2: timer@502e0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0000 0x14>; + interrupts = <16>; clocks = <&sysclk K210_CLK_TIMER1>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER1>; }; - timer2: timer@502f0000 { + timer3: timer@502e0014 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0014 0x114>; + interrupts = <17>; + clocks = <&sysclk K210_CLK_TIMER1>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER1>; + }; + + timer4: timer@502f0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502F0000 0x14>; + interrupts = <18>; + clocks = <&sysclk K210_CLK_TIMER2>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER2>; + }; + + timer5: timer@502f0014 { compatible = "snps,dw-apb-timer"; - reg = <0x502F0000 0x100>; - interrupts = <18>, <19>; + reg = <0x502F0014 0x14>; + interrupts = <19>; clocks = <&sysclk K210_CLK_TIMER2>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk";