| Message ID | 20220629141000.18111-9-johan+linaro@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: qcom: Add support for SC8280XP and SA8540P | expand |
On Wed, Jun 29, 2022 at 04:09:58PM +0200, Johan Hovold wrote: > The kernel is not a devicetree validator and does not need to re-encode > information which is already available in the devicetree. > > This is specifically true for the optional PCIe clocks, some of which > are really interconnect clocks. > > Treat also the 2.7.0 optional clocks as truly optional instead of > maintaining a list of clocks per compatible (including two compatible > strings for the two identical controllers on sm8450) just to validate > the devicetree. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 28 ++++---------------------- > 1 file changed, 4 insertions(+), 24 deletions(-) I guess this depends on patch 6, but looks like a good cleanup. Reviewed-by: Rob Herring <robh@kernel.org>
On Wed, Jun 29, 2022 at 04:09:58PM +0200, Johan Hovold wrote: > The kernel is not a devicetree validator and does not need to re-encode > information which is already available in the devicetree. > > This is specifically true for the optional PCIe clocks, some of which > are really interconnect clocks. > > Treat also the 2.7.0 optional clocks as truly optional instead of > maintaining a list of clocks per compatible (including two compatible > strings for the two identical controllers on sm8450) just to validate > the devicetree. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 28 ++++---------------------- > 1 file changed, 4 insertions(+), 24 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 8ab88e5743da..1a564f624bb1 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -189,10 +189,6 @@ struct qcom_pcie_ops { > > struct qcom_pcie_cfg { > const struct qcom_pcie_ops *ops; > - unsigned int has_tbu_clk:1; > - unsigned int has_ddrss_sf_tbu_clk:1; > - unsigned int has_aggre0_clk:1; > - unsigned int has_aggre1_clk:1; > }; > > struct qcom_pcie { > @@ -1140,14 +1136,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > res->clks[idx++].id = "bus_master"; > res->clks[idx++].id = "bus_slave"; > res->clks[idx++].id = "slave_q2a"; > - if (pcie->cfg->has_tbu_clk) > - res->clks[idx++].id = "tbu"; > - if (pcie->cfg->has_ddrss_sf_tbu_clk) > - res->clks[idx++].id = "ddrss_sf_tbu"; > - if (pcie->cfg->has_aggre0_clk) > - res->clks[idx++].id = "aggre0"; > - if (pcie->cfg->has_aggre1_clk) > - res->clks[idx++].id = "aggre1"; > > num_clks = idx; > > @@ -1155,6 +1143,10 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > if (ret < 0) > return ret; > > + res->clks[idx++].id = "tbu"; > + res->clks[idx++].id = "ddrss_sf_tbu"; > + res->clks[idx++].id = "aggre0"; > + res->clks[idx++].id = "aggre1"; > res->clks[idx++].id = "noc_aggr_4"; > res->clks[idx++].id = "noc_aggr_south_sf"; > res->clks[idx++].id = "cnoc_qx"; > @@ -1463,17 +1455,14 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { > > static const struct qcom_pcie_cfg sa8540p_cfg = { > .ops = &ops_1_9_0, > - .has_ddrss_sf_tbu_clk = true, > }; > > static const struct qcom_pcie_cfg sc8280xp_cfg = { > .ops = &ops_1_9_0, > - .has_ddrss_sf_tbu_clk = true, > }; > > static const struct qcom_pcie_cfg sdm845_cfg = { > .ops = &ops_2_7_0, > - .has_tbu_clk = true, > }; > > static const struct qcom_pcie_cfg sm8150_cfg = { > @@ -1485,31 +1474,22 @@ static const struct qcom_pcie_cfg sm8150_cfg = { > > static const struct qcom_pcie_cfg sm8250_cfg = { > .ops = &ops_1_9_0, > - .has_tbu_clk = true, > - .has_ddrss_sf_tbu_clk = true, > }; > > static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { > .ops = &ops_1_9_0, > - .has_ddrss_sf_tbu_clk = true, > - .has_aggre0_clk = true, > - .has_aggre1_clk = true, > }; > > static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { > .ops = &ops_1_9_0, > - .has_ddrss_sf_tbu_clk = true, > - .has_aggre1_clk = true, > }; > > static const struct qcom_pcie_cfg sc7280_cfg = { > .ops = &ops_1_9_0, > - .has_tbu_clk = true, > }; > > static const struct qcom_pcie_cfg sc8180x_cfg = { > .ops = &ops_1_9_0, > - .has_tbu_clk = true, > }; > > static const struct dw_pcie_ops dw_pcie_ops = { > -- > 2.35.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8ab88e5743da..1a564f624bb1 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -189,10 +189,6 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; - unsigned int has_tbu_clk:1; - unsigned int has_ddrss_sf_tbu_clk:1; - unsigned int has_aggre0_clk:1; - unsigned int has_aggre1_clk:1; }; struct qcom_pcie { @@ -1140,14 +1136,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "bus_master"; res->clks[idx++].id = "bus_slave"; res->clks[idx++].id = "slave_q2a"; - if (pcie->cfg->has_tbu_clk) - res->clks[idx++].id = "tbu"; - if (pcie->cfg->has_ddrss_sf_tbu_clk) - res->clks[idx++].id = "ddrss_sf_tbu"; - if (pcie->cfg->has_aggre0_clk) - res->clks[idx++].id = "aggre0"; - if (pcie->cfg->has_aggre1_clk) - res->clks[idx++].id = "aggre1"; num_clks = idx; @@ -1155,6 +1143,10 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; + res->clks[idx++].id = "tbu"; + res->clks[idx++].id = "ddrss_sf_tbu"; + res->clks[idx++].id = "aggre0"; + res->clks[idx++].id = "aggre1"; res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; @@ -1463,17 +1455,14 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sa8540p_cfg = { .ops = &ops_1_9_0, - .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sc8280xp_cfg = { .ops = &ops_1_9_0, - .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, - .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8150_cfg = { @@ -1485,31 +1474,22 @@ static const struct qcom_pcie_cfg sm8150_cfg = { static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, - .has_tbu_clk = true, - .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, - .has_ddrss_sf_tbu_clk = true, - .has_aggre0_clk = true, - .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, - .has_ddrss_sf_tbu_clk = true, - .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, - .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sc8180x_cfg = { .ops = &ops_1_9_0, - .has_tbu_clk = true, }; static const struct dw_pcie_ops dw_pcie_ops = {
The kernel is not a devicetree validator and does not need to re-encode information which is already available in the devicetree. This is specifically true for the optional PCIe clocks, some of which are really interconnect clocks. Treat also the 2.7.0 optional clocks as truly optional instead of maintaining a list of clocks per compatible (including two compatible strings for the two identical controllers on sm8450) just to validate the devicetree. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 28 ++++---------------------- 1 file changed, 4 insertions(+), 24 deletions(-)