| Message ID | 20220610092414.1816571-2-claudiu.beznea@microchip.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | power: reset: at91-reset: add support for sama7g5 | expand |
On 10.06.2022 12:24, Claudiu Beznea wrote: > Use generic name for reset controller of AT91 devices to comply with > DT specifications. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Applied to at91-dt, thanks! > --- > arch/arm/boot/dts/at91sam9260.dtsi | 2 +- > arch/arm/boot/dts/at91sam9261.dtsi | 2 +- > arch/arm/boot/dts/at91sam9263.dtsi | 2 +- > arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- > arch/arm/boot/dts/at91sam9n12.dtsi | 2 +- > arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- > arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- > arch/arm/boot/dts/sam9x60.dtsi | 2 +- > arch/arm/boot/dts/sama5d2.dtsi | 2 +- > arch/arm/boot/dts/sama5d3.dtsi | 2 +- > arch/arm/boot/dts/sama5d4.dtsi | 2 +- > 11 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi > index 7368347c9357..9d9820db9482 100644 > --- a/arch/arm/boot/dts/at91sam9260.dtsi > +++ b/arch/arm/boot/dts/at91sam9260.dtsi > @@ -123,7 +123,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_xtal", "main_xtal"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9260-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; > diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi > index 7adc36ca8a46..259aca565305 100644 > --- a/arch/arm/boot/dts/at91sam9261.dtsi > +++ b/arch/arm/boot/dts/at91sam9261.dtsi > @@ -603,7 +603,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_xtal", "main_xtal"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9260-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&slow_xtal>; > diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi > index fe45d96239c9..c080df8c2312 100644 > --- a/arch/arm/boot/dts/at91sam9263.dtsi > +++ b/arch/arm/boot/dts/at91sam9263.dtsi > @@ -151,7 +151,7 @@ tcb0: timer@fff7c000 { > clock-names = "t0_clk", "slow_clk"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9260-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&slow_xtal>; > diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi > index 2ab730fd6472..09794561c7ce 100644 > --- a/arch/arm/boot/dts/at91sam9g45.dtsi > +++ b/arch/arm/boot/dts/at91sam9g45.dtsi > @@ -137,7 +137,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_clk", "main_xtal"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9g45-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi > index 0785389f5507..556f35ce49e3 100644 > --- a/arch/arm/boot/dts/at91sam9n12.dtsi > +++ b/arch/arm/boot/dts/at91sam9n12.dtsi > @@ -126,7 +126,7 @@ pmc: pmc@fffffc00 { > interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; > }; > > - rstc@fffffe00 { > + reset-controller@fffffe00 { > compatible = "atmel,at91sam9g45-rstc"; > reg = <0xfffffe00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi > index 730d1182c73e..12c634811820 100644 > --- a/arch/arm/boot/dts/at91sam9rl.dtsi > +++ b/arch/arm/boot/dts/at91sam9rl.dtsi > @@ -766,7 +766,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_clk", "main_xtal"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9260-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi > index 395e883644cd..ea3b11336c79 100644 > --- a/arch/arm/boot/dts/at91sam9x5.dtsi > +++ b/arch/arm/boot/dts/at91sam9x5.dtsi > @@ -134,7 +134,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_clk", "main_xtal"; > }; > > - reset_controller: rstc@fffffe00 { > + reset_controller: reset-controller@fffffe00 { > compatible = "atmel,at91sam9g45-rstc"; > reg = <0xfffffe00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi > index c328b67bea0c..6b1d4492444a 100644 > --- a/arch/arm/boot/dts/sam9x60.dtsi > +++ b/arch/arm/boot/dts/sam9x60.dtsi > @@ -667,7 +667,7 @@ pmc: pmc@fffffc00 { > clock-names = "td_slck", "md_slck", "main_xtal"; > }; > > - reset_controller: rstc@fffffe00 { > + reset_controller: reset-controller@fffffe00 { > compatible = "microchip,sam9x60-rstc"; > reg = <0xfffffe00 0x10>; > clocks = <&clk32k 0>; > diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi > index 89c71d419f82..60977bfd8563 100644 > --- a/arch/arm/boot/dts/sama5d2.dtsi > +++ b/arch/arm/boot/dts/sama5d2.dtsi > @@ -660,7 +660,7 @@ securam: sram@f8044000 { > ranges = <0 0xf8044000 0x1420>; > }; > > - reset_controller: rstc@f8048000 { > + reset_controller: reset-controller@f8048000 { > compatible = "atmel,sama5d3-rstc"; > reg = <0xf8048000 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi > index 8fa423c52592..2d0935ad2225 100644 > --- a/arch/arm/boot/dts/sama5d3.dtsi > +++ b/arch/arm/boot/dts/sama5d3.dtsi > @@ -1003,7 +1003,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_clk", "main_xtal"; > }; > > - reset_controller: rstc@fffffe00 { > + reset_controller: reset-controller@fffffe00 { > compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; > reg = <0xfffffe00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi > index 7b9242664875..1e5c01898ccf 100644 > --- a/arch/arm/boot/dts/sama5d4.dtsi > +++ b/arch/arm/boot/dts/sama5d4.dtsi > @@ -726,7 +726,7 @@ pmecc: ecc-engine@ffffc070 { > }; > }; > > - reset_controller: rstc@fc068600 { > + reset_controller: reset-controller@fc068600 { > compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; > reg = <0xfc068600 0x10>; > clocks = <&clk32k>;
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 7368347c9357..9d9820db9482 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -123,7 +123,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 7adc36ca8a46..259aca565305 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -603,7 +603,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index fe45d96239c9..c080df8c2312 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -151,7 +151,7 @@ tcb0: timer@fff7c000 { clock-names = "t0_clk", "slow_clk"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 2ab730fd6472..09794561c7ce 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -137,7 +137,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 0785389f5507..556f35ce49e3 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -126,7 +126,7 @@ pmc: pmc@fffffc00 { interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; - rstc@fffffe00 { + reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 730d1182c73e..12c634811820 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -766,7 +766,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 395e883644cd..ea3b11336c79 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -134,7 +134,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index c328b67bea0c..6b1d4492444a 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -667,7 +667,7 @@ pmc: pmc@fffffc00 { clock-names = "td_slck", "md_slck", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "microchip,sam9x60-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k 0>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 89c71d419f82..60977bfd8563 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -660,7 +660,7 @@ securam: sram@f8044000 { ranges = <0 0xf8044000 0x1420>; }; - reset_controller: rstc@f8048000 { + reset_controller: reset-controller@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 8fa423c52592..2d0935ad2225 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1003,7 +1003,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 7b9242664875..1e5c01898ccf 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -726,7 +726,7 @@ pmecc: ecc-engine@ffffc070 { }; }; - reset_controller: rstc@fc068600 { + reset_controller: reset-controller@fc068600 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; clocks = <&clk32k>;