diff mbox series

[v5,9/9] ARM: dts: at91: sama7g5: add reset-controller node

Message ID 20220610092414.1816571-10-claudiu.beznea@microchip.com (mailing list archive)
State Handled Elsewhere, archived
Headers show
Series power: reset: at91-reset: add support for sama7g5 | expand

Commit Message

Claudiu Beznea June 10, 2022, 9:24 a.m. UTC 
Add reset controller node.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Claudiu Beznea July 4, 2022, 6:47 a.m. UTC | #1 
On 10.06.2022 12:24, Claudiu Beznea wrote:
> Add reset controller node.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Applied to at91-dt, thanks!

> ---
>  arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
> index a37e3a80392d..bb6d71e6dfeb 100644
> --- a/arch/arm/boot/dts/sama7g5.dtsi
> +++ b/arch/arm/boot/dts/sama7g5.dtsi
> @@ -198,6 +198,13 @@ pmc: pmc@e0018000 {
>  			clock-names = "td_slck", "md_slck", "main_xtal";
>  		};
>  
> +		reset_controller: reset-controller@e001d000 {
> +			compatible = "microchip,sama7g5-rstc";
> +			reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
> +			#reset-cells = <1>;
> +			clocks = <&clk32k 0>;
> +		};
> +
>  		shdwc: shdwc@e001d010 {
>  			compatible = "microchip,sama7g5-shdwc", "syscon";
>  			reg = <0xe001d010 0x10>;
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index a37e3a80392d..bb6d71e6dfeb 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -198,6 +198,13 @@  pmc: pmc@e0018000 {
 			clock-names = "td_slck", "md_slck", "main_xtal";
 		};
 
+		reset_controller: reset-controller@e001d000 {
+			compatible = "microchip,sama7g5-rstc";
+			reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
+			#reset-cells = <1>;
+			clocks = <&clk32k 0>;
+		};
+
 		shdwc: shdwc@e001d010 {
 			compatible = "microchip,sama7g5-shdwc", "syscon";
 			reg = <0xe001d010 0x10>;