| Message ID | 20220705114032.22787-3-johan+linaro@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | arm64: dts: qcom: QMP PHY fixes | expand |
On 05/07/2022 14:40, Johan Hovold wrote: > Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+)
On 05/07/2022 14:40, Johan Hovold wrote: > Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index 53e0b57c13e4..f45a6cca397f 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -1892,6 +1892,8 @@ pcie0_lane: phy@1c06200 { > clock-names = "pipe0"; > > #phy-cells = <0>; > + > + #clock-cells = <0>; > clock-output-names = "pcie_0_pipe_clk"; > }; > }; > @@ -1998,6 +2000,8 @@ pcie1_lane: phy@1c0e200 { > clock-names = "pipe0"; > > #phy-cells = <0>; > + > + #clock-cells = <0>; > clock-output-names = "pcie_1_pipe_clk"; > }; > }; > @@ -2104,6 +2108,8 @@ pcie2_lane: phy@1c16200 { > clock-names = "pipe0"; > > #phy-cells = <0>; > + > + #clock-cells = <0>; > clock-output-names = "pcie_2_pipe_clk"; > }; > };
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 53e0b57c13e4..f45a6cca397f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1892,6 +1892,8 @@ pcie0_lane: phy@1c06200 { clock-names = "pipe0"; #phy-cells = <0>; + + #clock-cells = <0>; clock-output-names = "pcie_0_pipe_clk"; }; }; @@ -1998,6 +2000,8 @@ pcie1_lane: phy@1c0e200 { clock-names = "pipe0"; #phy-cells = <0>; + + #clock-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; }; }; @@ -2104,6 +2108,8 @@ pcie2_lane: phy@1c16200 { clock-names = "pipe0"; #phy-cells = <0>; + + #clock-cells = <0>; clock-output-names = "pcie_2_pipe_clk"; }; };
Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)