| Message ID | 20220621163326.16858-3-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/3] dt-bindings: clock: add pcm reset for ipq806x lcc | expand |
On Tue, 21 Jun 2022 at 19:33, Christian Marangi <ansuelsmth@gmail.com> wrote: > > Convert lcc-ipq806x driver to parent_data API. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > --- > v2: > - Fix Sob tag > > drivers/clk/qcom/lcc-ipq806x.c | 79 +++++++++++++++++++--------------- > 1 file changed, 44 insertions(+), 35 deletions(-) > > diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c > index ba90bebba597..c07ca8dc6e3a 100644 > --- a/drivers/clk/qcom/lcc-ipq806x.c > +++ b/drivers/clk/qcom/lcc-ipq806x.c > @@ -24,6 +24,10 @@ > #include "clk-regmap-mux.h" > #include "reset.h" > > +static const struct clk_parent_data gcc_pxo[] = { > + { .fw_name = "pxo", .name = "pxo" }, I think you'd use .name = "pxo_board" here. You don't need to use the interim clock. > +}; > + > static struct clk_pll pll4 = { > .l_reg = 0x4, > .m_reg = 0x8, > @@ -34,7 +38,7 @@ static struct clk_pll pll4 = { > .status_bit = 16, > .clkr.hw.init = &(struct clk_init_data){ > .name = "pll4", > - .parent_names = (const char *[]){ "pxo" }, > + .parent_data = gcc_pxo, > .num_parents = 1, Could you please either inline the gcc_pxo here (yes, it's ugly, but it works for small arrays) or use ARRAY_SIZE here. > .ops = &clk_pll_ops, > }, > @@ -64,9 +68,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = { > { P_PLL4, 2 } > }; > > -static const char * const lcc_pxo_pll4[] = { > - "pxo", > - "pll4_vote", > +static const struct clk_parent_data lcc_pxo_pll4[] = { > + { .fw_name = "pxo", .name = "pxo" }, > + { .fw_name = "pll4_vote", .name = "pll4_vote" }, > }; > > static struct freq_tbl clk_tbl_aif_mi2s[] = { > @@ -131,18 +135,14 @@ static struct clk_rcg mi2s_osr_src = { > .enable_mask = BIT(9), > .hw.init = &(struct clk_init_data){ > .name = "mi2s_osr_src", > - .parent_names = lcc_pxo_pll4, > - .num_parents = 2, > + .parent_data = lcc_pxo_pll4, > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > .ops = &clk_rcg_ops, > .flags = CLK_SET_RATE_GATE, > }, > }, > }; > > -static const char * const lcc_mi2s_parents[] = { > - "mi2s_osr_src", > -}; > - > static struct clk_branch mi2s_osr_clk = { > .halt_reg = 0x50, > .halt_bit = 1, > @@ -152,7 +152,9 @@ static struct clk_branch mi2s_osr_clk = { > .enable_mask = BIT(17), > .hw.init = &(struct clk_init_data){ > .name = "mi2s_osr_clk", > - .parent_names = lcc_mi2s_parents, > + .parent_hws = (const struct clk_hw*[]){ > + &mi2s_osr_src.clkr.hw, > + }, > .num_parents = 1, > .ops = &clk_branch_ops, > .flags = CLK_SET_RATE_PARENT, > @@ -167,7 +169,9 @@ static struct clk_regmap_div mi2s_div_clk = { > .clkr = { > .hw.init = &(struct clk_init_data){ > .name = "mi2s_div_clk", > - .parent_names = lcc_mi2s_parents, > + .parent_hws = (const struct clk_hw*[]){ > + &mi2s_osr_src.clkr.hw, > + }, > .num_parents = 1, > .ops = &clk_regmap_div_ops, > }, > @@ -183,7 +187,9 @@ static struct clk_branch mi2s_bit_div_clk = { > .enable_mask = BIT(15), > .hw.init = &(struct clk_init_data){ > .name = "mi2s_bit_div_clk", > - .parent_names = (const char *[]){ "mi2s_div_clk" }, > + .parent_hws = (const struct clk_hw*[]){ > + &mi2s_div_clk.clkr.hw, > + }, > .num_parents = 1, > .ops = &clk_branch_ops, > .flags = CLK_SET_RATE_PARENT, > @@ -191,6 +197,10 @@ static struct clk_branch mi2s_bit_div_clk = { > }, > }; > > +static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { > + { .hw = &mi2s_bit_div_clk.clkr.hw, }, > + { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, > +}; > > static struct clk_regmap_mux mi2s_bit_clk = { > .reg = 0x48, > @@ -199,11 +209,8 @@ static struct clk_regmap_mux mi2s_bit_clk = { > .clkr = { > .hw.init = &(struct clk_init_data){ > .name = "mi2s_bit_clk", > - .parent_names = (const char *[]){ > - "mi2s_bit_div_clk", > - "mi2s_codec_clk", > - }, > - .num_parents = 2, > + .parent_data = lcc_mi2s_bit_div_codec_clk, > + .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), > .ops = &clk_regmap_mux_closest_ops, > .flags = CLK_SET_RATE_PARENT, > }, > @@ -245,8 +252,8 @@ static struct clk_rcg pcm_src = { > .enable_mask = BIT(9), > .hw.init = &(struct clk_init_data){ > .name = "pcm_src", > - .parent_names = lcc_pxo_pll4, > - .num_parents = 2, > + .parent_data = lcc_pxo_pll4, > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > .ops = &clk_rcg_ops, > .flags = CLK_SET_RATE_GATE, > }, > @@ -262,7 +269,9 @@ static struct clk_branch pcm_clk_out = { > .enable_mask = BIT(11), > .hw.init = &(struct clk_init_data){ > .name = "pcm_clk_out", > - .parent_names = (const char *[]){ "pcm_src" }, > + .parent_hws = (const struct clk_hw*[]){ > + &pcm_src.clkr.hw, > + }, > .num_parents = 1, > .ops = &clk_branch_ops, > .flags = CLK_SET_RATE_PARENT, > @@ -270,6 +279,11 @@ static struct clk_branch pcm_clk_out = { > }, > }; > > +static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { > + { .hw = &pcm_clk_out.clkr.hw, }, > + { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, > +}; > + > static struct clk_regmap_mux pcm_clk = { > .reg = 0x54, > .shift = 10, > @@ -277,11 +291,8 @@ static struct clk_regmap_mux pcm_clk = { > .clkr = { > .hw.init = &(struct clk_init_data){ > .name = "pcm_clk", > - .parent_names = (const char *[]){ > - "pcm_clk_out", > - "pcm_codec_clk", > - }, > - .num_parents = 2, > + .parent_data = lcc_pcm_clk_out_codec_clk, > + .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), > .ops = &clk_regmap_mux_closest_ops, > .flags = CLK_SET_RATE_PARENT, > }, > @@ -325,18 +336,14 @@ static struct clk_rcg spdif_src = { > .enable_mask = BIT(9), > .hw.init = &(struct clk_init_data){ > .name = "spdif_src", > - .parent_names = lcc_pxo_pll4, > - .num_parents = 2, > + .parent_data = lcc_pxo_pll4, > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > .ops = &clk_rcg_ops, > .flags = CLK_SET_RATE_GATE, > }, > }, > }; > > -static const char * const lcc_spdif_parents[] = { > - "spdif_src", > -}; > - > static struct clk_branch spdif_clk = { > .halt_reg = 0xd4, > .halt_bit = 1, > @@ -346,7 +353,9 @@ static struct clk_branch spdif_clk = { > .enable_mask = BIT(12), > .hw.init = &(struct clk_init_data){ > .name = "spdif_clk", > - .parent_names = lcc_spdif_parents, > + .parent_hws = (const struct clk_hw*[]){ > + &spdif_src.clkr.hw, > + }, > .num_parents = 1, > .ops = &clk_branch_ops, > .flags = CLK_SET_RATE_PARENT, > @@ -384,8 +393,8 @@ static struct clk_rcg ahbix_clk = { > .enable_mask = BIT(11), > .hw.init = &(struct clk_init_data){ > .name = "ahbix", > - .parent_names = lcc_pxo_pll4, > - .num_parents = 2, > + .parent_data = lcc_pxo_pll4, > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > .ops = &clk_rcg_lcc_ops, > }, > }, > -- > 2.36.1 >
On Tue, Jun 21, 2022 at 08:15:57PM +0300, Dmitry Baryshkov wrote: > On Tue, 21 Jun 2022 at 19:33, Christian Marangi <ansuelsmth@gmail.com> wrote: > > > > Convert lcc-ipq806x driver to parent_data API. > > > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > > --- > > v2: > > - Fix Sob tag > > > > drivers/clk/qcom/lcc-ipq806x.c | 79 +++++++++++++++++++--------------- > > 1 file changed, 44 insertions(+), 35 deletions(-) > > > > diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c > > index ba90bebba597..c07ca8dc6e3a 100644 > > --- a/drivers/clk/qcom/lcc-ipq806x.c > > +++ b/drivers/clk/qcom/lcc-ipq806x.c > > @@ -24,6 +24,10 @@ > > #include "clk-regmap-mux.h" > > #include "reset.h" > > > > +static const struct clk_parent_data gcc_pxo[] = { > > + { .fw_name = "pxo", .name = "pxo" }, > > I think you'd use .name = "pxo_board" here. You don't need to use the > interim clock. > In gcc and in the rest of this driver we use pxo. Wonder what is right? > > +}; > > + > > static struct clk_pll pll4 = { > > .l_reg = 0x4, > > .m_reg = 0x8, > > @@ -34,7 +38,7 @@ static struct clk_pll pll4 = { > > .status_bit = 16, > > .clkr.hw.init = &(struct clk_init_data){ > > .name = "pll4", > > - .parent_names = (const char *[]){ "pxo" }, > > + .parent_data = gcc_pxo, > > .num_parents = 1, > > Could you please either inline the gcc_pxo here (yes, it's ugly, but > it works for small arrays) or use ARRAY_SIZE here. > Yes will inline gcc_pxo. > > .ops = &clk_pll_ops, > > }, > > @@ -64,9 +68,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = { > > { P_PLL4, 2 } > > }; > > > > -static const char * const lcc_pxo_pll4[] = { > > - "pxo", > > - "pll4_vote", > > +static const struct clk_parent_data lcc_pxo_pll4[] = { > > + { .fw_name = "pxo", .name = "pxo" }, > > + { .fw_name = "pll4_vote", .name = "pll4_vote" }, > > }; > > > > static struct freq_tbl clk_tbl_aif_mi2s[] = { > > @@ -131,18 +135,14 @@ static struct clk_rcg mi2s_osr_src = { > > .enable_mask = BIT(9), > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_osr_src", > > - .parent_names = lcc_pxo_pll4, > > - .num_parents = 2, > > + .parent_data = lcc_pxo_pll4, > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > .ops = &clk_rcg_ops, > > .flags = CLK_SET_RATE_GATE, > > }, > > }, > > }; > > > > -static const char * const lcc_mi2s_parents[] = { > > - "mi2s_osr_src", > > -}; > > - > > static struct clk_branch mi2s_osr_clk = { > > .halt_reg = 0x50, > > .halt_bit = 1, > > @@ -152,7 +152,9 @@ static struct clk_branch mi2s_osr_clk = { > > .enable_mask = BIT(17), > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_osr_clk", > > - .parent_names = lcc_mi2s_parents, > > + .parent_hws = (const struct clk_hw*[]){ > > + &mi2s_osr_src.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_branch_ops, > > .flags = CLK_SET_RATE_PARENT, > > @@ -167,7 +169,9 @@ static struct clk_regmap_div mi2s_div_clk = { > > .clkr = { > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_div_clk", > > - .parent_names = lcc_mi2s_parents, > > + .parent_hws = (const struct clk_hw*[]){ > > + &mi2s_osr_src.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_regmap_div_ops, > > }, > > @@ -183,7 +187,9 @@ static struct clk_branch mi2s_bit_div_clk = { > > .enable_mask = BIT(15), > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_bit_div_clk", > > - .parent_names = (const char *[]){ "mi2s_div_clk" }, > > + .parent_hws = (const struct clk_hw*[]){ > > + &mi2s_div_clk.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_branch_ops, > > .flags = CLK_SET_RATE_PARENT, > > @@ -191,6 +197,10 @@ static struct clk_branch mi2s_bit_div_clk = { > > }, > > }; > > > > +static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { > > + { .hw = &mi2s_bit_div_clk.clkr.hw, }, > > + { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, > > +}; > > > > static struct clk_regmap_mux mi2s_bit_clk = { > > .reg = 0x48, > > @@ -199,11 +209,8 @@ static struct clk_regmap_mux mi2s_bit_clk = { > > .clkr = { > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_bit_clk", > > - .parent_names = (const char *[]){ > > - "mi2s_bit_div_clk", > > - "mi2s_codec_clk", > > - }, > > - .num_parents = 2, > > + .parent_data = lcc_mi2s_bit_div_codec_clk, > > + .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), > > .ops = &clk_regmap_mux_closest_ops, > > .flags = CLK_SET_RATE_PARENT, > > }, > > @@ -245,8 +252,8 @@ static struct clk_rcg pcm_src = { > > .enable_mask = BIT(9), > > .hw.init = &(struct clk_init_data){ > > .name = "pcm_src", > > - .parent_names = lcc_pxo_pll4, > > - .num_parents = 2, > > + .parent_data = lcc_pxo_pll4, > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > .ops = &clk_rcg_ops, > > .flags = CLK_SET_RATE_GATE, > > }, > > @@ -262,7 +269,9 @@ static struct clk_branch pcm_clk_out = { > > .enable_mask = BIT(11), > > .hw.init = &(struct clk_init_data){ > > .name = "pcm_clk_out", > > - .parent_names = (const char *[]){ "pcm_src" }, > > + .parent_hws = (const struct clk_hw*[]){ > > + &pcm_src.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_branch_ops, > > .flags = CLK_SET_RATE_PARENT, > > @@ -270,6 +279,11 @@ static struct clk_branch pcm_clk_out = { > > }, > > }; > > > > +static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { > > + { .hw = &pcm_clk_out.clkr.hw, }, > > + { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, > > +}; > > + > > static struct clk_regmap_mux pcm_clk = { > > .reg = 0x54, > > .shift = 10, > > @@ -277,11 +291,8 @@ static struct clk_regmap_mux pcm_clk = { > > .clkr = { > > .hw.init = &(struct clk_init_data){ > > .name = "pcm_clk", > > - .parent_names = (const char *[]){ > > - "pcm_clk_out", > > - "pcm_codec_clk", > > - }, > > - .num_parents = 2, > > + .parent_data = lcc_pcm_clk_out_codec_clk, > > + .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), > > .ops = &clk_regmap_mux_closest_ops, > > .flags = CLK_SET_RATE_PARENT, > > }, > > @@ -325,18 +336,14 @@ static struct clk_rcg spdif_src = { > > .enable_mask = BIT(9), > > .hw.init = &(struct clk_init_data){ > > .name = "spdif_src", > > - .parent_names = lcc_pxo_pll4, > > - .num_parents = 2, > > + .parent_data = lcc_pxo_pll4, > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > .ops = &clk_rcg_ops, > > .flags = CLK_SET_RATE_GATE, > > }, > > }, > > }; > > > > -static const char * const lcc_spdif_parents[] = { > > - "spdif_src", > > -}; > > - > > static struct clk_branch spdif_clk = { > > .halt_reg = 0xd4, > > .halt_bit = 1, > > @@ -346,7 +353,9 @@ static struct clk_branch spdif_clk = { > > .enable_mask = BIT(12), > > .hw.init = &(struct clk_init_data){ > > .name = "spdif_clk", > > - .parent_names = lcc_spdif_parents, > > + .parent_hws = (const struct clk_hw*[]){ > > + &spdif_src.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_branch_ops, > > .flags = CLK_SET_RATE_PARENT, > > @@ -384,8 +393,8 @@ static struct clk_rcg ahbix_clk = { > > .enable_mask = BIT(11), > > .hw.init = &(struct clk_init_data){ > > .name = "ahbix", > > - .parent_names = lcc_pxo_pll4, > > - .num_parents = 2, > > + .parent_data = lcc_pxo_pll4, > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > .ops = &clk_rcg_lcc_ops, > > }, > > }, > > -- > > 2.36.1 > > > > > -- > With best wishes > Dmitry
On Tue, 21 Jun 2022 at 23:23, Christian Marangi <ansuelsmth@gmail.com> wrote: > > On Tue, Jun 21, 2022 at 08:15:57PM +0300, Dmitry Baryshkov wrote: > > On Tue, 21 Jun 2022 at 19:33, Christian Marangi <ansuelsmth@gmail.com> wrote: > > > > > > Convert lcc-ipq806x driver to parent_data API. > > > > > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > > > --- > > > v2: > > > - Fix Sob tag > > > > > > drivers/clk/qcom/lcc-ipq806x.c | 79 +++++++++++++++++++--------------- > > > 1 file changed, 44 insertions(+), 35 deletions(-) > > > > > > diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c > > > index ba90bebba597..c07ca8dc6e3a 100644 > > > --- a/drivers/clk/qcom/lcc-ipq806x.c > > > +++ b/drivers/clk/qcom/lcc-ipq806x.c > > > @@ -24,6 +24,10 @@ > > > #include "clk-regmap-mux.h" > > > #include "reset.h" > > > > > > +static const struct clk_parent_data gcc_pxo[] = { > > > + { .fw_name = "pxo", .name = "pxo" }, > > > > I think you'd use .name = "pxo_board" here. You don't need to use the > > interim clock. > > > > In gcc and in the rest of this driver we use pxo. Wonder what is right? I'd use .fw_name = "pxo", .name = "pxo_board", like the rest of drivers do. > > > > +}; > > > + > > > static struct clk_pll pll4 = { > > > .l_reg = 0x4, > > > .m_reg = 0x8, > > > @@ -34,7 +38,7 @@ static struct clk_pll pll4 = { > > > .status_bit = 16, > > > .clkr.hw.init = &(struct clk_init_data){ > > > .name = "pll4", > > > - .parent_names = (const char *[]){ "pxo" }, > > > + .parent_data = gcc_pxo, > > > .num_parents = 1, > > > > Could you please either inline the gcc_pxo here (yes, it's ugly, but > > it works for small arrays) or use ARRAY_SIZE here. > > > > Yes will inline gcc_pxo. > > > > .ops = &clk_pll_ops, > > > }, > > > @@ -64,9 +68,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = { > > > { P_PLL4, 2 } > > > }; > > > > > > -static const char * const lcc_pxo_pll4[] = { > > > - "pxo", > > > - "pll4_vote", > > > +static const struct clk_parent_data lcc_pxo_pll4[] = { > > > + { .fw_name = "pxo", .name = "pxo" }, > > > + { .fw_name = "pll4_vote", .name = "pll4_vote" }, > > > }; > > > > > > static struct freq_tbl clk_tbl_aif_mi2s[] = { > > > @@ -131,18 +135,14 @@ static struct clk_rcg mi2s_osr_src = { > > > .enable_mask = BIT(9), > > > .hw.init = &(struct clk_init_data){ > > > .name = "mi2s_osr_src", > > > - .parent_names = lcc_pxo_pll4, > > > - .num_parents = 2, > > > + .parent_data = lcc_pxo_pll4, > > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > > .ops = &clk_rcg_ops, > > > .flags = CLK_SET_RATE_GATE, > > > }, > > > }, > > > }; > > > > > > -static const char * const lcc_mi2s_parents[] = { > > > - "mi2s_osr_src", > > > -}; > > > - > > > static struct clk_branch mi2s_osr_clk = { > > > .halt_reg = 0x50, > > > .halt_bit = 1, > > > @@ -152,7 +152,9 @@ static struct clk_branch mi2s_osr_clk = { > > > .enable_mask = BIT(17), > > > .hw.init = &(struct clk_init_data){ > > > .name = "mi2s_osr_clk", > > > - .parent_names = lcc_mi2s_parents, > > > + .parent_hws = (const struct clk_hw*[]){ > > > + &mi2s_osr_src.clkr.hw, > > > + }, > > > .num_parents = 1, > > > .ops = &clk_branch_ops, > > > .flags = CLK_SET_RATE_PARENT, > > > @@ -167,7 +169,9 @@ static struct clk_regmap_div mi2s_div_clk = { > > > .clkr = { > > > .hw.init = &(struct clk_init_data){ > > > .name = "mi2s_div_clk", > > > - .parent_names = lcc_mi2s_parents, > > > + .parent_hws = (const struct clk_hw*[]){ > > > + &mi2s_osr_src.clkr.hw, > > > + }, > > > .num_parents = 1, > > > .ops = &clk_regmap_div_ops, > > > }, > > > @@ -183,7 +187,9 @@ static struct clk_branch mi2s_bit_div_clk = { > > > .enable_mask = BIT(15), > > > .hw.init = &(struct clk_init_data){ > > > .name = "mi2s_bit_div_clk", > > > - .parent_names = (const char *[]){ "mi2s_div_clk" }, > > > + .parent_hws = (const struct clk_hw*[]){ > > > + &mi2s_div_clk.clkr.hw, > > > + }, > > > .num_parents = 1, > > > .ops = &clk_branch_ops, > > > .flags = CLK_SET_RATE_PARENT, > > > @@ -191,6 +197,10 @@ static struct clk_branch mi2s_bit_div_clk = { > > > }, > > > }; > > > > > > +static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { > > > + { .hw = &mi2s_bit_div_clk.clkr.hw, }, > > > + { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, > > > +}; > > > > > > static struct clk_regmap_mux mi2s_bit_clk = { > > > .reg = 0x48, > > > @@ -199,11 +209,8 @@ static struct clk_regmap_mux mi2s_bit_clk = { > > > .clkr = { > > > .hw.init = &(struct clk_init_data){ > > > .name = "mi2s_bit_clk", > > > - .parent_names = (const char *[]){ > > > - "mi2s_bit_div_clk", > > > - "mi2s_codec_clk", > > > - }, > > > - .num_parents = 2, > > > + .parent_data = lcc_mi2s_bit_div_codec_clk, > > > + .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), > > > .ops = &clk_regmap_mux_closest_ops, > > > .flags = CLK_SET_RATE_PARENT, > > > }, > > > @@ -245,8 +252,8 @@ static struct clk_rcg pcm_src = { > > > .enable_mask = BIT(9), > > > .hw.init = &(struct clk_init_data){ > > > .name = "pcm_src", > > > - .parent_names = lcc_pxo_pll4, > > > - .num_parents = 2, > > > + .parent_data = lcc_pxo_pll4, > > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > > .ops = &clk_rcg_ops, > > > .flags = CLK_SET_RATE_GATE, > > > }, > > > @@ -262,7 +269,9 @@ static struct clk_branch pcm_clk_out = { > > > .enable_mask = BIT(11), > > > .hw.init = &(struct clk_init_data){ > > > .name = "pcm_clk_out", > > > - .parent_names = (const char *[]){ "pcm_src" }, > > > + .parent_hws = (const struct clk_hw*[]){ > > > + &pcm_src.clkr.hw, > > > + }, > > > .num_parents = 1, > > > .ops = &clk_branch_ops, > > > .flags = CLK_SET_RATE_PARENT, > > > @@ -270,6 +279,11 @@ static struct clk_branch pcm_clk_out = { > > > }, > > > }; > > > > > > +static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { > > > + { .hw = &pcm_clk_out.clkr.hw, }, > > > + { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, > > > +}; > > > + > > > static struct clk_regmap_mux pcm_clk = { > > > .reg = 0x54, > > > .shift = 10, > > > @@ -277,11 +291,8 @@ static struct clk_regmap_mux pcm_clk = { > > > .clkr = { > > > .hw.init = &(struct clk_init_data){ > > > .name = "pcm_clk", > > > - .parent_names = (const char *[]){ > > > - "pcm_clk_out", > > > - "pcm_codec_clk", > > > - }, > > > - .num_parents = 2, > > > + .parent_data = lcc_pcm_clk_out_codec_clk, > > > + .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), > > > .ops = &clk_regmap_mux_closest_ops, > > > .flags = CLK_SET_RATE_PARENT, > > > }, > > > @@ -325,18 +336,14 @@ static struct clk_rcg spdif_src = { > > > .enable_mask = BIT(9), > > > .hw.init = &(struct clk_init_data){ > > > .name = "spdif_src", > > > - .parent_names = lcc_pxo_pll4, > > > - .num_parents = 2, > > > + .parent_data = lcc_pxo_pll4, > > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > > .ops = &clk_rcg_ops, > > > .flags = CLK_SET_RATE_GATE, > > > }, > > > }, > > > }; > > > > > > -static const char * const lcc_spdif_parents[] = { > > > - "spdif_src", > > > -}; > > > - > > > static struct clk_branch spdif_clk = { > > > .halt_reg = 0xd4, > > > .halt_bit = 1, > > > @@ -346,7 +353,9 @@ static struct clk_branch spdif_clk = { > > > .enable_mask = BIT(12), > > > .hw.init = &(struct clk_init_data){ > > > .name = "spdif_clk", > > > - .parent_names = lcc_spdif_parents, > > > + .parent_hws = (const struct clk_hw*[]){ > > > + &spdif_src.clkr.hw, > > > + }, > > > .num_parents = 1, > > > .ops = &clk_branch_ops, > > > .flags = CLK_SET_RATE_PARENT, > > > @@ -384,8 +393,8 @@ static struct clk_rcg ahbix_clk = { > > > .enable_mask = BIT(11), > > > .hw.init = &(struct clk_init_data){ > > > .name = "ahbix", > > > - .parent_names = lcc_pxo_pll4, > > > - .num_parents = 2, > > > + .parent_data = lcc_pxo_pll4, > > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > > .ops = &clk_rcg_lcc_ops, > > > }, > > > }, > > > -- > > > 2.36.1 > > > > > > > > > -- > > With best wishes > > Dmitry > > -- > Ansuel
On Tue, Jun 21, 2022 at 11:43:10PM +0300, Dmitry Baryshkov wrote: > On Tue, 21 Jun 2022 at 23:23, Christian Marangi <ansuelsmth@gmail.com> wrote: > > > > On Tue, Jun 21, 2022 at 08:15:57PM +0300, Dmitry Baryshkov wrote: > > > On Tue, 21 Jun 2022 at 19:33, Christian Marangi <ansuelsmth@gmail.com> wrote: > > > > > > > > Convert lcc-ipq806x driver to parent_data API. > > > > > > > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > > > > --- > > > > v2: > > > > - Fix Sob tag > > > > > > > > drivers/clk/qcom/lcc-ipq806x.c | 79 +++++++++++++++++++--------------- > > > > 1 file changed, 44 insertions(+), 35 deletions(-) > > > > > > > > diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c > > > > index ba90bebba597..c07ca8dc6e3a 100644 > > > > --- a/drivers/clk/qcom/lcc-ipq806x.c > > > > +++ b/drivers/clk/qcom/lcc-ipq806x.c > > > > @@ -24,6 +24,10 @@ > > > > #include "clk-regmap-mux.h" > > > > #include "reset.h" > > > > > > > > +static const struct clk_parent_data gcc_pxo[] = { > > > > + { .fw_name = "pxo", .name = "pxo" }, > > > > > > I think you'd use .name = "pxo_board" here. You don't need to use the > > > interim clock. > > > > > > > In gcc and in the rest of this driver we use pxo. Wonder what is right? > > I'd use .fw_name = "pxo", .name = "pxo_board", like the rest of drivers do. > Will do the change, but I need an explaination... Is the use of pxo_board correct? I'm sending a patch that sets the pxo_board fixed clock in dts to output "pxo". The only clock that still use pxo_board is rpm, everything else at least for ipq806x use pxo and i'm sending a patch to use pxo for rpm. Considering pxo is always present and pxo_board should be dropped because every ipq806x driver use "pxo". What is correct naming pxo or pxo_board? I assume pxo right? > > > > > > +}; > > > > + > > > > static struct clk_pll pll4 = { > > > > .l_reg = 0x4, > > > > .m_reg = 0x8, > > > > @@ -34,7 +38,7 @@ static struct clk_pll pll4 = { > > > > .status_bit = 16, > > > > .clkr.hw.init = &(struct clk_init_data){ > > > > .name = "pll4", > > > > - .parent_names = (const char *[]){ "pxo" }, > > > > + .parent_data = gcc_pxo, > > > > .num_parents = 1, > > > > > > Could you please either inline the gcc_pxo here (yes, it's ugly, but > > > it works for small arrays) or use ARRAY_SIZE here. > > > > > > > Yes will inline gcc_pxo. > > > > > > .ops = &clk_pll_ops, > > > > }, > > > > @@ -64,9 +68,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = { > > > > { P_PLL4, 2 } > > > > }; > > > > > > > > -static const char * const lcc_pxo_pll4[] = { > > > > - "pxo", > > > > - "pll4_vote", > > > > +static const struct clk_parent_data lcc_pxo_pll4[] = { > > > > + { .fw_name = "pxo", .name = "pxo" }, > > > > + { .fw_name = "pll4_vote", .name = "pll4_vote" }, > > > > }; > > > > > > > > static struct freq_tbl clk_tbl_aif_mi2s[] = { > > > > @@ -131,18 +135,14 @@ static struct clk_rcg mi2s_osr_src = { > > > > .enable_mask = BIT(9), > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "mi2s_osr_src", > > > > - .parent_names = lcc_pxo_pll4, > > > > - .num_parents = 2, > > > > + .parent_data = lcc_pxo_pll4, > > > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > > > .ops = &clk_rcg_ops, > > > > .flags = CLK_SET_RATE_GATE, > > > > }, > > > > }, > > > > }; > > > > > > > > -static const char * const lcc_mi2s_parents[] = { > > > > - "mi2s_osr_src", > > > > -}; > > > > - > > > > static struct clk_branch mi2s_osr_clk = { > > > > .halt_reg = 0x50, > > > > .halt_bit = 1, > > > > @@ -152,7 +152,9 @@ static struct clk_branch mi2s_osr_clk = { > > > > .enable_mask = BIT(17), > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "mi2s_osr_clk", > > > > - .parent_names = lcc_mi2s_parents, > > > > + .parent_hws = (const struct clk_hw*[]){ > > > > + &mi2s_osr_src.clkr.hw, > > > > + }, > > > > .num_parents = 1, > > > > .ops = &clk_branch_ops, > > > > .flags = CLK_SET_RATE_PARENT, > > > > @@ -167,7 +169,9 @@ static struct clk_regmap_div mi2s_div_clk = { > > > > .clkr = { > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "mi2s_div_clk", > > > > - .parent_names = lcc_mi2s_parents, > > > > + .parent_hws = (const struct clk_hw*[]){ > > > > + &mi2s_osr_src.clkr.hw, > > > > + }, > > > > .num_parents = 1, > > > > .ops = &clk_regmap_div_ops, > > > > }, > > > > @@ -183,7 +187,9 @@ static struct clk_branch mi2s_bit_div_clk = { > > > > .enable_mask = BIT(15), > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "mi2s_bit_div_clk", > > > > - .parent_names = (const char *[]){ "mi2s_div_clk" }, > > > > + .parent_hws = (const struct clk_hw*[]){ > > > > + &mi2s_div_clk.clkr.hw, > > > > + }, > > > > .num_parents = 1, > > > > .ops = &clk_branch_ops, > > > > .flags = CLK_SET_RATE_PARENT, > > > > @@ -191,6 +197,10 @@ static struct clk_branch mi2s_bit_div_clk = { > > > > }, > > > > }; > > > > > > > > +static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { > > > > + { .hw = &mi2s_bit_div_clk.clkr.hw, }, > > > > + { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, > > > > +}; > > > > > > > > static struct clk_regmap_mux mi2s_bit_clk = { > > > > .reg = 0x48, > > > > @@ -199,11 +209,8 @@ static struct clk_regmap_mux mi2s_bit_clk = { > > > > .clkr = { > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "mi2s_bit_clk", > > > > - .parent_names = (const char *[]){ > > > > - "mi2s_bit_div_clk", > > > > - "mi2s_codec_clk", > > > > - }, > > > > - .num_parents = 2, > > > > + .parent_data = lcc_mi2s_bit_div_codec_clk, > > > > + .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), > > > > .ops = &clk_regmap_mux_closest_ops, > > > > .flags = CLK_SET_RATE_PARENT, > > > > }, > > > > @@ -245,8 +252,8 @@ static struct clk_rcg pcm_src = { > > > > .enable_mask = BIT(9), > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "pcm_src", > > > > - .parent_names = lcc_pxo_pll4, > > > > - .num_parents = 2, > > > > + .parent_data = lcc_pxo_pll4, > > > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > > > .ops = &clk_rcg_ops, > > > > .flags = CLK_SET_RATE_GATE, > > > > }, > > > > @@ -262,7 +269,9 @@ static struct clk_branch pcm_clk_out = { > > > > .enable_mask = BIT(11), > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "pcm_clk_out", > > > > - .parent_names = (const char *[]){ "pcm_src" }, > > > > + .parent_hws = (const struct clk_hw*[]){ > > > > + &pcm_src.clkr.hw, > > > > + }, > > > > .num_parents = 1, > > > > .ops = &clk_branch_ops, > > > > .flags = CLK_SET_RATE_PARENT, > > > > @@ -270,6 +279,11 @@ static struct clk_branch pcm_clk_out = { > > > > }, > > > > }; > > > > > > > > +static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { > > > > + { .hw = &pcm_clk_out.clkr.hw, }, > > > > + { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, > > > > +}; > > > > + > > > > static struct clk_regmap_mux pcm_clk = { > > > > .reg = 0x54, > > > > .shift = 10, > > > > @@ -277,11 +291,8 @@ static struct clk_regmap_mux pcm_clk = { > > > > .clkr = { > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "pcm_clk", > > > > - .parent_names = (const char *[]){ > > > > - "pcm_clk_out", > > > > - "pcm_codec_clk", > > > > - }, > > > > - .num_parents = 2, > > > > + .parent_data = lcc_pcm_clk_out_codec_clk, > > > > + .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), > > > > .ops = &clk_regmap_mux_closest_ops, > > > > .flags = CLK_SET_RATE_PARENT, > > > > }, > > > > @@ -325,18 +336,14 @@ static struct clk_rcg spdif_src = { > > > > .enable_mask = BIT(9), > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "spdif_src", > > > > - .parent_names = lcc_pxo_pll4, > > > > - .num_parents = 2, > > > > + .parent_data = lcc_pxo_pll4, > > > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > > > .ops = &clk_rcg_ops, > > > > .flags = CLK_SET_RATE_GATE, > > > > }, > > > > }, > > > > }; > > > > > > > > -static const char * const lcc_spdif_parents[] = { > > > > - "spdif_src", > > > > -}; > > > > - > > > > static struct clk_branch spdif_clk = { > > > > .halt_reg = 0xd4, > > > > .halt_bit = 1, > > > > @@ -346,7 +353,9 @@ static struct clk_branch spdif_clk = { > > > > .enable_mask = BIT(12), > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "spdif_clk", > > > > - .parent_names = lcc_spdif_parents, > > > > + .parent_hws = (const struct clk_hw*[]){ > > > > + &spdif_src.clkr.hw, > > > > + }, > > > > .num_parents = 1, > > > > .ops = &clk_branch_ops, > > > > .flags = CLK_SET_RATE_PARENT, > > > > @@ -384,8 +393,8 @@ static struct clk_rcg ahbix_clk = { > > > > .enable_mask = BIT(11), > > > > .hw.init = &(struct clk_init_data){ > > > > .name = "ahbix", > > > > - .parent_names = lcc_pxo_pll4, > > > > - .num_parents = 2, > > > > + .parent_data = lcc_pxo_pll4, > > > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > > > .ops = &clk_rcg_lcc_ops, > > > > }, > > > > }, > > > > -- > > > > 2.36.1 > > > > > > > > > > > > > -- > > > With best wishes > > > Dmitry > > > > -- > > Ansuel > > > > -- > With best wishes > Dmitry
On Tue, 5 Jul 2022 at 23:48, Christian Marangi <ansuelsmth@gmail.com> wrote: > > On Tue, Jun 21, 2022 at 11:43:10PM +0300, Dmitry Baryshkov wrote: > > On Tue, 21 Jun 2022 at 23:23, Christian Marangi <ansuelsmth@gmail.com> wrote: > > > > > > On Tue, Jun 21, 2022 at 08:15:57PM +0300, Dmitry Baryshkov wrote: > > > > On Tue, 21 Jun 2022 at 19:33, Christian Marangi <ansuelsmth@gmail.com> wrote: > > > > > > > > > > Convert lcc-ipq806x driver to parent_data API. > > > > > > > > > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > > > > > --- > > > > > v2: > > > > > - Fix Sob tag > > > > > > > > > > drivers/clk/qcom/lcc-ipq806x.c | 79 +++++++++++++++++++--------------- > > > > > 1 file changed, 44 insertions(+), 35 deletions(-) > > > > > > > > > > diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c > > > > > index ba90bebba597..c07ca8dc6e3a 100644 > > > > > --- a/drivers/clk/qcom/lcc-ipq806x.c > > > > > +++ b/drivers/clk/qcom/lcc-ipq806x.c > > > > > @@ -24,6 +24,10 @@ > > > > > #include "clk-regmap-mux.h" > > > > > #include "reset.h" > > > > > > > > > > +static const struct clk_parent_data gcc_pxo[] = { > > > > > + { .fw_name = "pxo", .name = "pxo" }, > > > > > > > > I think you'd use .name = "pxo_board" here. You don't need to use the > > > > interim clock. > > > > > > > > > > In gcc and in the rest of this driver we use pxo. Wonder what is right? > > > > I'd use .fw_name = "pxo", .name = "pxo_board", like the rest of drivers do. > > > > Will do the change, but I need an explaination... Is the use of > pxo_board correct? > > I'm sending a patch that sets the pxo_board fixed clock in dts to output > "pxo". The only clock that still use pxo_board is rpm, everything else > at least for ipq806x use pxo and i'm sending a patch to use pxo for rpm. > > Considering pxo is always present and pxo_board should be dropped > because every ipq806x driver use "pxo". > > What is correct naming pxo or pxo_board? I assume pxo right? This might be not the case for the ipq806x, but here is the story for all other (old) platforms: - gcc driver manually registered pxo/cxo/xo fixed factor clocks. - Then we started adding *xo_board clocks to the DT, as they represent the external oscillators - PXO clock consumers receive a clocks entry with clock-names = "pxo" which points to the pxo_board - All clock drivers are now being switched to use .fw_name = "pxo", .name = "pxo_board" to use the DT-defined pxo_board clock. Hopefully at some point we can then drop the manually registered pxo clock and always use the DT-based one.
On Wed, Jul 06, 2022 at 10:34:04AM +0300, Dmitry Baryshkov wrote: > On Tue, 5 Jul 2022 at 23:48, Christian Marangi <ansuelsmth@gmail.com> wrote: > > > > On Tue, Jun 21, 2022 at 11:43:10PM +0300, Dmitry Baryshkov wrote: > > > On Tue, 21 Jun 2022 at 23:23, Christian Marangi <ansuelsmth@gmail.com> wrote: > > > > > > > > On Tue, Jun 21, 2022 at 08:15:57PM +0300, Dmitry Baryshkov wrote: > > > > > On Tue, 21 Jun 2022 at 19:33, Christian Marangi <ansuelsmth@gmail.com> wrote: > > > > > > > > > > > > Convert lcc-ipq806x driver to parent_data API. > > > > > > > > > > > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > > > > > > --- > > > > > > v2: > > > > > > - Fix Sob tag > > > > > > > > > > > > drivers/clk/qcom/lcc-ipq806x.c | 79 +++++++++++++++++++--------------- > > > > > > 1 file changed, 44 insertions(+), 35 deletions(-) > > > > > > > > > > > > diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c > > > > > > index ba90bebba597..c07ca8dc6e3a 100644 > > > > > > --- a/drivers/clk/qcom/lcc-ipq806x.c > > > > > > +++ b/drivers/clk/qcom/lcc-ipq806x.c > > > > > > @@ -24,6 +24,10 @@ > > > > > > #include "clk-regmap-mux.h" > > > > > > #include "reset.h" > > > > > > > > > > > > +static const struct clk_parent_data gcc_pxo[] = { > > > > > > + { .fw_name = "pxo", .name = "pxo" }, > > > > > > > > > > I think you'd use .name = "pxo_board" here. You don't need to use the > > > > > interim clock. > > > > > > > > > > > > > In gcc and in the rest of this driver we use pxo. Wonder what is right? > > > > > > I'd use .fw_name = "pxo", .name = "pxo_board", like the rest of drivers do. > > > > > > > Will do the change, but I need an explaination... Is the use of > > pxo_board correct? > > > > I'm sending a patch that sets the pxo_board fixed clock in dts to output > > "pxo". The only clock that still use pxo_board is rpm, everything else > > at least for ipq806x use pxo and i'm sending a patch to use pxo for rpm. > > > > Considering pxo is always present and pxo_board should be dropped > > because every ipq806x driver use "pxo". > > > > What is correct naming pxo or pxo_board? I assume pxo right? > > This might be not the case for the ipq806x, but here is the story for > all other (old) platforms: > - gcc driver manually registered pxo/cxo/xo fixed factor clocks. > - Then we started adding *xo_board clocks to the DT, as they represent > the external oscillators > - PXO clock consumers receive a clocks entry with clock-names = "pxo" > which points to the pxo_board > - All clock drivers are now being switched to use .fw_name = "pxo", > .name = "pxo_board" to use the DT-defined pxo_board clock. > > Hopefully at some point we can then drop the manually registered pxo > clock and always use the DT-based one. > Okok. I got confused since looking at the code factor clock is really just a hack to handle both driver that use pxo_board and pxo cause from what I notice it's the same clock with different naming. Sooo keep using pxo_board with the fact that pxo is always present seems to be redundant but if that's the pattern then I will just keep pxo_board in .name where it's used. > -- > With best wishes > Dmitry
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c index ba90bebba597..c07ca8dc6e3a 100644 --- a/drivers/clk/qcom/lcc-ipq806x.c +++ b/drivers/clk/qcom/lcc-ipq806x.c @@ -24,6 +24,10 @@ #include "clk-regmap-mux.h" #include "reset.h" +static const struct clk_parent_data gcc_pxo[] = { + { .fw_name = "pxo", .name = "pxo" }, +}; + static struct clk_pll pll4 = { .l_reg = 0x4, .m_reg = 0x8, @@ -34,7 +38,7 @@ static struct clk_pll pll4 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll4", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -64,9 +68,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = { { P_PLL4, 2 } }; -static const char * const lcc_pxo_pll4[] = { - "pxo", - "pll4_vote", +static const struct clk_parent_data lcc_pxo_pll4[] = { + { .fw_name = "pxo", .name = "pxo" }, + { .fw_name = "pll4_vote", .name = "pll4_vote" }, }; static struct freq_tbl clk_tbl_aif_mi2s[] = { @@ -131,18 +135,14 @@ static struct clk_rcg mi2s_osr_src = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "mi2s_osr_src", - .parent_names = lcc_pxo_pll4, - .num_parents = 2, + .parent_data = lcc_pxo_pll4, + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, }, }; -static const char * const lcc_mi2s_parents[] = { - "mi2s_osr_src", -}; - static struct clk_branch mi2s_osr_clk = { .halt_reg = 0x50, .halt_bit = 1, @@ -152,7 +152,9 @@ static struct clk_branch mi2s_osr_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "mi2s_osr_clk", - .parent_names = lcc_mi2s_parents, + .parent_hws = (const struct clk_hw*[]){ + &mi2s_osr_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -167,7 +169,9 @@ static struct clk_regmap_div mi2s_div_clk = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "mi2s_div_clk", - .parent_names = lcc_mi2s_parents, + .parent_hws = (const struct clk_hw*[]){ + &mi2s_osr_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_regmap_div_ops, }, @@ -183,7 +187,9 @@ static struct clk_branch mi2s_bit_div_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "mi2s_bit_div_clk", - .parent_names = (const char *[]){ "mi2s_div_clk" }, + .parent_hws = (const struct clk_hw*[]){ + &mi2s_div_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -191,6 +197,10 @@ static struct clk_branch mi2s_bit_div_clk = { }, }; +static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { + { .hw = &mi2s_bit_div_clk.clkr.hw, }, + { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, +}; static struct clk_regmap_mux mi2s_bit_clk = { .reg = 0x48, @@ -199,11 +209,8 @@ static struct clk_regmap_mux mi2s_bit_clk = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "mi2s_bit_clk", - .parent_names = (const char *[]){ - "mi2s_bit_div_clk", - "mi2s_codec_clk", - }, - .num_parents = 2, + .parent_data = lcc_mi2s_bit_div_codec_clk, + .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -245,8 +252,8 @@ static struct clk_rcg pcm_src = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcm_src", - .parent_names = lcc_pxo_pll4, - .num_parents = 2, + .parent_data = lcc_pxo_pll4, + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -262,7 +269,9 @@ static struct clk_branch pcm_clk_out = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcm_clk_out", - .parent_names = (const char *[]){ "pcm_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcm_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -270,6 +279,11 @@ static struct clk_branch pcm_clk_out = { }, }; +static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { + { .hw = &pcm_clk_out.clkr.hw, }, + { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, +}; + static struct clk_regmap_mux pcm_clk = { .reg = 0x54, .shift = 10, @@ -277,11 +291,8 @@ static struct clk_regmap_mux pcm_clk = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "pcm_clk", - .parent_names = (const char *[]){ - "pcm_clk_out", - "pcm_codec_clk", - }, - .num_parents = 2, + .parent_data = lcc_pcm_clk_out_codec_clk, + .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -325,18 +336,14 @@ static struct clk_rcg spdif_src = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "spdif_src", - .parent_names = lcc_pxo_pll4, - .num_parents = 2, + .parent_data = lcc_pxo_pll4, + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, }, }; -static const char * const lcc_spdif_parents[] = { - "spdif_src", -}; - static struct clk_branch spdif_clk = { .halt_reg = 0xd4, .halt_bit = 1, @@ -346,7 +353,9 @@ static struct clk_branch spdif_clk = { .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .name = "spdif_clk", - .parent_names = lcc_spdif_parents, + .parent_hws = (const struct clk_hw*[]){ + &spdif_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -384,8 +393,8 @@ static struct clk_rcg ahbix_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "ahbix", - .parent_names = lcc_pxo_pll4, - .num_parents = 2, + .parent_data = lcc_pxo_pll4, + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), .ops = &clk_rcg_lcc_ops, }, },
Convert lcc-ipq806x driver to parent_data API. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- v2: - Fix Sob tag drivers/clk/qcom/lcc-ipq806x.c | 79 +++++++++++++++++++--------------- 1 file changed, 44 insertions(+), 35 deletions(-)