| Message ID | 20220706213255.1473069-6-thierry.reding@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | tegra: Add support for MGBE controller | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Guessing tree name failed - patch did not apply |
On Wed, 06 Jul 2022 23:32:51 +0200, Thierry Reding wrote: > From: Bhadram Varka <vbhadram@nvidia.com> > > Add device-tree binding documentation for the Multi-Gigabit Ethernet > (MGBE) controller found on NVIDIA Tegra234 SoCs. > > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v3: > - add macsec and macsec-ns interrupt names > - improve mdio bus node description > - drop power-domains description > - improve bindings title > > Changes in v2: > - add supported PHY modes > - change to dual license > > .../bindings/net/nvidia,tegra234-mgbe.yaml | 169 ++++++++++++++++++ > 1 file changed, 169 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Error: Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.example.dts:53.34-35 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:383: Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1404: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Wed, Jul 06, 2022 at 10:59:49PM -0600, Rob Herring wrote: > On Wed, 06 Jul 2022 23:32:51 +0200, Thierry Reding wrote: > > From: Bhadram Varka <vbhadram@nvidia.com> > > > > Add device-tree binding documentation for the Multi-Gigabit Ethernet > > (MGBE) controller found on NVIDIA Tegra234 SoCs. > > > > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > > Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> > > Signed-off-by: Thierry Reding <treding@nvidia.com> > > --- > > Changes in v3: > > - add macsec and macsec-ns interrupt names > > - improve mdio bus node description > > - drop power-domains description > > - improve bindings title > > > > Changes in v2: > > - add supported PHY modes > > - change to dual license > > > > .../bindings/net/nvidia,tegra234-mgbe.yaml | 169 ++++++++++++++++++ > > 1 file changed, 169 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Error: Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.example.dts:53.34-35 syntax error > FATAL ERROR: Unable to parse input tree This is an error that you'd get if patch 3 is not applied. Not sure if I managed to confuse the bot somehow, but I cannot reproduce this if I apply the series on top of v5.19-rc1 or linux-next. Thierry
On 07/07/2022 08:17, Thierry Reding wrote: > On Wed, Jul 06, 2022 at 10:59:49PM -0600, Rob Herring wrote: >> On Wed, 06 Jul 2022 23:32:51 +0200, Thierry Reding wrote: >>> From: Bhadram Varka <vbhadram@nvidia.com> >>> >>> Add device-tree binding documentation for the Multi-Gigabit Ethernet >>> (MGBE) controller found on NVIDIA Tegra234 SoCs. >>> >>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> >>> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> >>> Signed-off-by: Thierry Reding <treding@nvidia.com> >>> --- >>> Changes in v3: >>> - add macsec and macsec-ns interrupt names >>> - improve mdio bus node description >>> - drop power-domains description >>> - improve bindings title >>> >>> Changes in v2: >>> - add supported PHY modes >>> - change to dual license >>> >>> .../bindings/net/nvidia,tegra234-mgbe.yaml | 169 ++++++++++++++++++ >>> 1 file changed, 169 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml >>> >> >> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' >> on your patch (DT_CHECKER_FLAGS is new in v5.13): >> >> yamllint warnings/errors: >> >> dtschema/dtc warnings/errors: >> Error: Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.example.dts:53.34-35 syntax error >> FATAL ERROR: Unable to parse input tree > > This is an error that you'd get if patch 3 is not applied. Not sure if I > managed to confuse the bot somehow, but I cannot reproduce this if I > apply the series on top of v5.19-rc1 or linux-next. Patch number 3 does not apply on v5.19-rc1 or linux-next, so maybe the bot (which applies on rc1) did not have it. Best regards, Krzysztof
On 06/07/2022 23:32, Thierry Reding wrote: > From: Bhadram Varka <vbhadram@nvidia.com> > > Add device-tree binding documentation for the Multi-Gigabit Ethernet > (MGBE) controller found on NVIDIA Tegra234 SoCs. > > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v3: > - add macsec and macsec-ns interrupt names > - improve mdio bus node description > - drop power-domains description > - improve bindings title > > Changes in v2: > - add supported PHY modes > - change to dual license > > .../bindings/net/nvidia,tegra234-mgbe.yaml | 169 ++++++++++++++++++ > 1 file changed, 169 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml > > diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml > new file mode 100644 > index 000000000000..3d242ef1ca57 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml > @@ -0,0 +1,169 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Tegra234 MGBE Multi-Gigabit Ethernet Controller > + > +maintainers: > + - Thierry Reding <treding@nvidia.com> > + - Jon Hunter <jonathanh@nvidia.com> > + > +properties: > + Drop the blank line. > + compatible: > + const: nvidia,tegra234-mgbe > + > + reg: > + minItems: 3 Drop minitems (equal to maxItems) > + maxItems: 3 > + > + reg-names: > + items: > + - const: hypervisor > + - const: mac > + - const: xpcs > + > + interrupts: > + minItems: 1 You need maxItems:3 > + > + interrupt-names: > + minItems: 1 > + items: > + - const: common > + - const: macsec-ns > + - const: macsec > + > + clocks: > + minItems: 12 Drop minItems > + maxItems: 12 > + > + clock-names: > + minItems: 12 > + maxItems: 12 Drop min/max and instead list the clocks in fixed order.. The order is always fixed, so below enum is not correct. > + contains: > + enum: > + - mgbe > + - mac > + - mac-divider > + - ptp-ref > + - rx-input-m > + - rx-input > + - tx > + - eee-pcs > + - rx-pcs-input > + - rx-pcs-m > + - rx-pcs > + - tx-pcs > + > + resets: > + minItems: 2 Drop minItems. > + maxItems: 2 > + > + reset-names: > + contains: > + enum: Same problem. > + - mac > + - pcs > + > + interconnects: > + items: > + - description: memory read client > + - description: memory write client > + > + interconnect-names: > + items: > + - const: dma-mem # read I propose to drop the comment - it is obvious from "interconnects" above. Best regards, Krzysztof
On Thu, Jul 07, 2022 at 08:53:32AM +0200, Krzysztof Kozlowski wrote: > On 07/07/2022 08:17, Thierry Reding wrote: > > On Wed, Jul 06, 2022 at 10:59:49PM -0600, Rob Herring wrote: > >> On Wed, 06 Jul 2022 23:32:51 +0200, Thierry Reding wrote: > >>> From: Bhadram Varka <vbhadram@nvidia.com> > >>> > >>> Add device-tree binding documentation for the Multi-Gigabit Ethernet > >>> (MGBE) controller found on NVIDIA Tegra234 SoCs. > >>> > >>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > >>> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> > >>> Signed-off-by: Thierry Reding <treding@nvidia.com> > >>> --- > >>> Changes in v3: > >>> - add macsec and macsec-ns interrupt names > >>> - improve mdio bus node description > >>> - drop power-domains description > >>> - improve bindings title > >>> > >>> Changes in v2: > >>> - add supported PHY modes > >>> - change to dual license > >>> > >>> .../bindings/net/nvidia,tegra234-mgbe.yaml | 169 ++++++++++++++++++ > >>> 1 file changed, 169 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml > >>> > >> > >> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > >> on your patch (DT_CHECKER_FLAGS is new in v5.13): > >> > >> yamllint warnings/errors: > >> > >> dtschema/dtc warnings/errors: > >> Error: Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.example.dts:53.34-35 syntax error > >> FATAL ERROR: Unable to parse input tree > > > > This is an error that you'd get if patch 3 is not applied. Not sure if I > > managed to confuse the bot somehow, but I cannot reproduce this if I > > apply the series on top of v5.19-rc1 or linux-next. > > Patch number 3 does not apply on v5.19-rc1 or linux-next, so maybe the > bot (which applies on rc1) did not have it. Good point. I'll rebase v4 on top of v5.19-rc1 then. This shouldn't cause a problem for net-next because there's no conflict there for patch 9. I did notice that the devicetree-bindings patchwork instance doesn't have all of the patches, so perhaps that tripped up the bot as well. Not sure what happened there, the linux-tegra instance has all 9 patches. Thierry
On Thu, Jul 07, 2022 at 08:56:49AM +0200, Krzysztof Kozlowski wrote: > On 06/07/2022 23:32, Thierry Reding wrote: [...] > > + - mac > > + - pcs > > + > > + interconnects: > > + items: > > + - description: memory read client > > + - description: memory write client > > + > > + interconnect-names: > > + items: > > + - const: dma-mem # read > > I propose to drop the comment - it is obvious from "interconnects" above. Yeah, fair enough. I've addressed all of the other comments in v4 as well. Thanks for the review! Thierry
diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml new file mode 100644 index 000000000000..3d242ef1ca57 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra234 MGBE Multi-Gigabit Ethernet Controller + +maintainers: + - Thierry Reding <treding@nvidia.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + + compatible: + const: nvidia,tegra234-mgbe + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: hypervisor + - const: mac + - const: xpcs + + interrupts: + minItems: 1 + + interrupt-names: + minItems: 1 + items: + - const: common + - const: macsec-ns + - const: macsec + + clocks: + minItems: 12 + maxItems: 12 + + clock-names: + minItems: 12 + maxItems: 12 + contains: + enum: + - mgbe + - mac + - mac-divider + - ptp-ref + - rx-input-m + - rx-input + - tx + - eee-pcs + - rx-pcs-input + - rx-pcs-m + - rx-pcs + - tx-pcs + + resets: + minItems: 2 + maxItems: 2 + + reset-names: + contains: + enum: + - mac + - pcs + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + phy-handle: true + + phy-mode: + contains: + enum: + - usxgmii + - 10gbase-kr + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + description: + Optional node for embedded MDIO controller. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - phy-handle + - phy-mode + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra234-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra234-mc.h> + #include <dt-bindings/power/tegra234-powergate.h> + #include <dt-bindings/reset/tegra234-reset.h> + + ethernet@6800000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06800000 0x10000>, + <0x06810000 0x10000>, + <0x068a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, + <&bpmp TEGRA234_CLK_MGBE0_MAC>, + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_TX>, + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, + <&bpmp TEGRA234_RESET_MGBE0_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; + + phy-handle = <&mgbe0_phy>; + phy-mode = "usxgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mgbe0_phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + + #phy-cells = <0>; + }; + }; + };