| Message ID | 20220708222743.27019-1-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | PCI: qcom: Enable clocks only after PARF_PHY setup for rev 2.1.0 | expand |
On Sat, Jul 09, 2022 at 12:27:43AM +0200, Christian Marangi wrote: > We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to > enable clocks and resets. This case the driver to never set to a ready > state with the error 'Phy link never came up'. > > This in fact is caused by the phy clock getting enabled before setting > the required bits in the PARF regs. > > A workaround for this was set but with this new discovery we can drop > the workaround and use a proper solution to the problem by just enabling > the clock only AFTER the PARF_PHY_CTRL bit is set. > > This correctly setup the pcie line and makes it usable even when a > bootloader leave the pcie line to a underfined state. Is "pcie" here a signal name? Maybe this refers to the "PCIe link"? > Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") > Cc: stable@vger.kernel.org # v5.4+ > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Thanks, I put this on https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git, pci/ctrl/qcom-pending branch (head 47b4ec9d2e60). Can you take a look and make sure I didn't mess up the conflict resolution with the rest of the series? > --- > drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++------ > 1 file changed, 4 insertions(+), 6 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 2ea13750b492..da13a66ced14 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -337,8 +337,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) > reset_control_assert(res->ext_reset); > reset_control_assert(res->phy_reset); > > - writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); > - > ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); > if (ret < 0) { > dev_err(dev, "cannot enable regulators\n"); > @@ -381,15 +379,15 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) > goto err_deassert_axi; > } > > - ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > - if (ret) > - goto err_clks; > - > /* enable PCIe clocks and resets */ > val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); > val &= ~BIT(0); > writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); > > + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > + if (ret) > + goto err_clks; > + > if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || > of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { > writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | > -- > 2.36.1 >
On Fri, Jul 08, 2022 at 06:01:55PM -0500, Bjorn Helgaas wrote: > On Sat, Jul 09, 2022 at 12:27:43AM +0200, Christian Marangi wrote: > > We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to > > enable clocks and resets. This case the driver to never set to a ready > > state with the error 'Phy link never came up'. > > > > This in fact is caused by the phy clock getting enabled before setting > > the required bits in the PARF regs. > > > > A workaround for this was set but with this new discovery we can drop > > the workaround and use a proper solution to the problem by just enabling > > the clock only AFTER the PARF_PHY_CTRL bit is set. > > > > This correctly setup the pcie line and makes it usable even when a > > bootloader leave the pcie line to a underfined state. > > Is "pcie" here a signal name? Maybe this refers to the "PCIe link"? > Hi, no i was referring to PCIe link. Fell free to fix it if it's not a problem (or if you want i can just resend) > > Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") > > Cc: stable@vger.kernel.org # v5.4+ > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > > Thanks, I put this on > https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git, > pci/ctrl/qcom-pending branch (head 47b4ec9d2e60). > > Can you take a look and make sure I didn't mess up the conflict > resolution with the rest of the series? Think something went wrong in the rebase as the patch fixup is reverted. 11946f8b6e77a6794c111aafef7772e9967d9a54 is still wrong. clk_bulk_prepare_enable must be after writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); so in the post init. > > > --- > > drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++------ > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > > index 2ea13750b492..da13a66ced14 100644 > > --- a/drivers/pci/controller/dwc/pcie-qcom.c > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > > @@ -337,8 +337,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) > > reset_control_assert(res->ext_reset); > > reset_control_assert(res->phy_reset); > > > > - writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); > > - > > ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); > > if (ret < 0) { > > dev_err(dev, "cannot enable regulators\n"); > > @@ -381,15 +379,15 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) > > goto err_deassert_axi; > > } > > > > - ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > > - if (ret) > > - goto err_clks; > > - > > /* enable PCIe clocks and resets */ > > val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); > > val &= ~BIT(0); > > writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); > > > > + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > > + if (ret) > > + goto err_clks; > > + > > if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || > > of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { > > writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | > > -- > > 2.36.1 > >
[+cc Robert since I resolved a conflict in his patch, -cc stable] On Sat, Jul 09, 2022 at 03:03:34AM +0200, Christian Marangi wrote: > On Fri, Jul 08, 2022 at 06:01:55PM -0500, Bjorn Helgaas wrote: > > On Sat, Jul 09, 2022 at 12:27:43AM +0200, Christian Marangi wrote: > > > We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to > > > enable clocks and resets. This case the driver to never set to a ready > > > state with the error 'Phy link never came up'. > > > > > > This in fact is caused by the phy clock getting enabled before setting > > > the required bits in the PARF regs. > > > > > > A workaround for this was set but with this new discovery we can drop > > > the workaround and use a proper solution to the problem by just enabling > > > the clock only AFTER the PARF_PHY_CTRL bit is set. > > > > > > This correctly setup the pcie line and makes it usable even when a > > > bootloader leave the pcie line to a underfined state. > > > > Is "pcie" here a signal name? Maybe this refers to the "PCIe link"? > > no i was referring to PCIe link. Fell free to fix it if it's not a > problem (or if you want i can just resend) I fixed it. > Think something went wrong in the rebase as the patch fixup is reverted. > > 11946f8b6e77a6794c111aafef7772e9967d9a54 is still wrong. > > clk_bulk_prepare_enable must be after > writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); > so in the post init. My error, sorry. I updated it, current head: 1a88605a3efd ("dt-bindings: PCI: qcom: Fix description typo") Robert, your patch that I updated is: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/commit/?h=pci/ctrl/qcom-pending&id=cdb32283bcf202d0db512abb80794056d44e7e9f It would still be nice to get an ack from one of the maintainers for this. Bjorn
On Mon, 11 Jul 2022 at 21:22, Bjorn Helgaas <helgaas@kernel.org> wrote: > > [+cc Robert since I resolved a conflict in his patch, -cc stable] > > On Sat, Jul 09, 2022 at 03:03:34AM +0200, Christian Marangi wrote: > > On Fri, Jul 08, 2022 at 06:01:55PM -0500, Bjorn Helgaas wrote: > > > On Sat, Jul 09, 2022 at 12:27:43AM +0200, Christian Marangi wrote: > > > > We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to > > > > enable clocks and resets. This case the driver to never set to a ready > > > > state with the error 'Phy link never came up'. > > > > > > > > This in fact is caused by the phy clock getting enabled before setting > > > > the required bits in the PARF regs. > > > > > > > > A workaround for this was set but with this new discovery we can drop > > > > the workaround and use a proper solution to the problem by just enabling > > > > the clock only AFTER the PARF_PHY_CTRL bit is set. > > > > > > > > This correctly setup the pcie line and makes it usable even when a > > > > bootloader leave the pcie line to a underfined state. > > > > > > Is "pcie" here a signal name? Maybe this refers to the "PCIe link"? > > > > no i was referring to PCIe link. Fell free to fix it if it's not a > > problem (or if you want i can just resend) > > I fixed it. > > > Think something went wrong in the rebase as the patch fixup is reverted. > > > > 11946f8b6e77a6794c111aafef7772e9967d9a54 is still wrong. > > > > clk_bulk_prepare_enable must be after > > writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); > > so in the post init. > > My error, sorry. I updated it, current head: > > 1a88605a3efd ("dt-bindings: PCI: qcom: Fix description typo") > > Robert, your patch that I updated is: > > https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/commit/?h=pci/ctrl/qcom-pending&id=cdb32283bcf202d0db512abb80794056d44e7e9f > > It would still be nice to get an ack from one of the maintainers for > this. Hi, Thanks, everybody for working on sorting this out. I understand, hopefully, somebody can take a look at it. BTW, happy to see IPQ60xx support made it in as IPQ807x can use it for Gen3. Regards, Robert > > Bjorn
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2ea13750b492..da13a66ced14 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -337,8 +337,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); - writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); - ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); if (ret < 0) { dev_err(dev, "cannot enable regulators\n"); @@ -381,15 +379,15 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_axi; } - ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); - if (ret) - goto err_clks; - /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0); writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + if (ret) + goto err_clks; + if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to enable clocks and resets. This case the driver to never set to a ready state with the error 'Phy link never came up'. This in fact is caused by the phy clock getting enabled before setting the required bits in the PARF regs. A workaround for this was set but with this new discovery we can drop the workaround and use a proper solution to the problem by just enabling the clock only AFTER the PARF_PHY_CTRL bit is set. This correctly setup the pcie line and makes it usable even when a bootloader leave the pcie line to a underfined state. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Cc: stable@vger.kernel.org # v5.4+ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)