| Message ID | 20220710111330.3920699-1-mail@conchuod.ie (mailing list archive) |
|---|---|
| Headers | show |
| Series | JH7100 Monitor Core | expand |
On Sun, 10 Jul 2022 at 13:13, Conor Dooley <mail@conchuod.ie> wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > Hey Emil, > > Had a go at adding that E24, made it an RFC b/c I am not sure if I got > the cache setup anywhere close to correct. I had a look in the SiFive > E24 docs & in [0] which said "16KB I-cache with 32 Byte cache line". > Didn't have anything else to go on, so I kept the same ratio between > lines/sets/size as other SiFive monitor cores, but since they're not > 32 bit I dunno if that's correct (IOW it is a wild guess). > > Hopefully you know better than I do.. Hi Conor, Thanks for the patch! Unfortunately I don't know any more, but I'm fine with adding this data for now. /Emil 1: https://sifive.cdn.prismic.io/sifive/dc408861-94ce-4d82-a704-caddec98609d_e24_core_complex_manual_21G3.pdf > Thanks, > Conor. > > 0: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf > > Conor Dooley (2): > dt-bindings: riscv: document the sifive e24 > riscv: dts: starfive: add the missing monitor core > > .../devicetree/bindings/riscv/cpus.yaml | 2 ++ > arch/riscv/boot/dts/starfive/jh7100.dtsi | 20 +++++++++++++++++++ > 2 files changed, 22 insertions(+) > > -- > 2.37.0 >
From: Conor Dooley <conor.dooley@microchip.com> Hey Emil, Had a go at adding that E24, made it an RFC b/c I am not sure if I got the cache setup anywhere close to correct. I had a look in the SiFive E24 docs & in [0] which said "16KB I-cache with 32 Byte cache line". Didn't have anything else to go on, so I kept the same ratio between lines/sets/size as other SiFive monitor cores, but since they're not 32 bit I dunno if that's correct (IOW it is a wild guess). Hopefully you know better than I do.. Thanks, Conor. 0: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Conor Dooley (2): dt-bindings: riscv: document the sifive e24 riscv: dts: starfive: add the missing monitor core .../devicetree/bindings/riscv/cpus.yaml | 2 ++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 20 +++++++++++++++++++ 2 files changed, 22 insertions(+)