| Message ID | 20220309151541.139511-2-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | viresh kumar |
| Headers | show |
| Series | Convert Qcom CPUFREQ HW binding to YAML | expand |
On Wed, Mar 09, 2022 at 08:45:40PM +0530, Manivannan Sadhasivam wrote: > Qcom CPUFREQ HW don't have the support for generic performance domains yet. > So use MediaTek CPUFREQ HW that has the support available in mainline. > > This also silences the below dtschema warnings for "cpufreq-qcom-hw.yaml": > > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: reg: [[305397760, 4096]] is too short > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: 'clocks' is a required property > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: 'clock-names' is a required property > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: '#freq-domain-cells' is a required property > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: '#performance-domain-cells' does not match any of the regexes: 'pinctrl-[0-9]+' > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > > Cc: Hector Yuan <hector.yuan@mediatek.com> > Cc: Sudeep Holla <sudeep.holla@arm.com> Thanks for fixing this. It seem to have slipped through the cracks. I had plans to push this once Mediatek driver was merged but totally forgot about it. Acked-by: Sudeep Holla <sudeep.holla@arm.com>
On Wed, 09 Mar 2022 20:45:40 +0530, Manivannan Sadhasivam wrote: > Qcom CPUFREQ HW don't have the support for generic performance domains yet. > So use MediaTek CPUFREQ HW that has the support available in mainline. > > This also silences the below dtschema warnings for "cpufreq-qcom-hw.yaml": > > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: reg: [[305397760, 4096]] is too short > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: 'clocks' is a required property > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: 'clock-names' is a required property > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: '#freq-domain-cells' is a required property > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: '#performance-domain-cells' does not match any of the regexes: 'pinctrl-[0-9]+' > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > > Cc: Hector Yuan <hector.yuan@mediatek.com> > Cc: Sudeep Holla <sudeep.holla@arm.com> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > .../bindings/dvfs/performance-domain.yaml | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
On Wed, Mar 09, 2022 at 08:45:40PM +0530, Manivannan Sadhasivam wrote: > Qcom CPUFREQ HW don't have the support for generic performance domains yet. > So use MediaTek CPUFREQ HW that has the support available in mainline. > > This also silences the below dtschema warnings for "cpufreq-qcom-hw.yaml": > > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: reg: [[305397760, 4096]] is too short > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: 'clocks' is a required property > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: 'clock-names' is a required property > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: '#freq-domain-cells' is a required property > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: '#performance-domain-cells' does not match any of the regexes: 'pinctrl-[0-9]+' > From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > > Cc: Hector Yuan <hector.yuan@mediatek.com> > Cc: Sudeep Holla <sudeep.holla@arm.com> Thanks for picking this up. Acked-by: Sudeep Holla <sudeep.holla@arm.com>
diff --git a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml index c8b91207f34d..9e0bcf1a89fe 100644 --- a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml +++ b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml @@ -52,10 +52,16 @@ additionalProperties: true examples: - | - performance: performance-controller@12340000 { - compatible = "qcom,cpufreq-hw"; - reg = <0x12340000 0x1000>; - #performance-domain-cells = <1>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + performance: performance-controller@11bc00 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + + #performance-domain-cells = <1>; + }; }; // The node above defines a performance controller that is a performance
Qcom CPUFREQ HW don't have the support for generic performance domains yet. So use MediaTek CPUFREQ HW that has the support available in mainline. This also silences the below dtschema warnings for "cpufreq-qcom-hw.yaml": Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: reg: [[305397760, 4096]] is too short From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: 'clocks' is a required property From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: 'clock-names' is a required property From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: '#freq-domain-cells' is a required property From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: performance-controller@12340000: '#performance-domain-cells' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml Cc: Hector Yuan <hector.yuan@mediatek.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- .../bindings/dvfs/performance-domain.yaml | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)