| Message ID | 20220715062550.789736-2-vishal.l.verma@intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl: add region management | expand |
Vishal Verma wrote: > Add a depth attribute to the cxl_port structure, that can be used for > calculating its distance from the root port, and will be needed for > interleave granularity calculations during region creation. > > Suggested-by: Dan Williams <dan.j.williams@intel.com> > Signed-off-by: Vishal Verma <vishal.l.verma@intel.com> Looks good, Reviewed-by: Dan Williams <dan.j.williams@intel.com>
diff --git a/cxl/lib/private.h b/cxl/lib/private.h index f6d4573..832a815 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -66,6 +66,7 @@ struct cxl_port { int decoders_init; int dports_init; int nr_dports; + int depth; struct cxl_ctx *ctx; struct cxl_bus *bus; enum cxl_port_type type; diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index be6bc2c..946cd4b 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -744,6 +744,7 @@ static int cxl_port_init(struct cxl_port *port, struct cxl_port *parent_port, port->type = type; port->parent = parent_port; port->type = type; + port->depth = parent_port ? parent_port->depth + 1 : 0; list_head_init(&port->child_ports); list_head_init(&port->endpoints);
Add a depth attribute to the cxl_port structure, that can be used for calculating its distance from the root port, and will be needed for interleave granularity calculations during region creation. Suggested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vishal Verma <vishal.l.verma@intel.com> --- cxl/lib/private.h | 1 + cxl/lib/libcxl.c | 1 + 2 files changed, 2 insertions(+)