Message ID | 20220730115758.16787-1-naveenm@marvell.com (mailing list archive) |
---|---|
Headers | show |
Series | Add PTP support for CN10K silicon | expand |
On Sat, 30 Jul 2022 17:27:54 +0530 Naveen Mamindlapalli wrote: > This patchset adds PTP support for CN10K silicon, specifically > to workaround few hardware issues and to add 1-step mode. Hi Richard, any thoughts on this one? We have to make a go/no-go decision on it for 6.0.
On Tue, 2 Aug 2022 12:14:39 -0700 Jakub Kicinski wrote: > On Sat, 30 Jul 2022 17:27:54 +0530 Naveen Mamindlapalli wrote: > > This patchset adds PTP support for CN10K silicon, specifically > > to workaround few hardware issues and to add 1-step mode. > > Hi Richard, any thoughts on this one? We have to make a go/no-go > decision on it for 6.0. Oh, well. These will have to wait until after the merge window then :(
On Tue, Aug 02, 2022 at 09:44:20PM -0700, Jakub Kicinski wrote: > On Tue, 2 Aug 2022 12:14:39 -0700 Jakub Kicinski wrote: > > On Sat, 30 Jul 2022 17:27:54 +0530 Naveen Mamindlapalli wrote: > > > This patchset adds PTP support for CN10K silicon, specifically > > > to workaround few hardware issues and to add 1-step mode. > > > > Hi Richard, any thoughts on this one? We have to make a go/no-go > > decision on it for 6.0. > > Oh, well. These will have to wait until after the merge window then :( FWIW - I'm okay with any PTP patches that are about specific hardware drivers. When I can, I'll review them for proper use of the core layer, locking, etc, but at the end of the day, only the people holding the data sheet know how to talk to the hardware. Patches that touch the core layer are another story. These need careful review by me and other. (Obviously) Thanks, Richard
On Wed, 3 Aug 2022 20:08:50 -0700 Richard Cochran wrote: > > Oh, well. These will have to wait until after the merge window then :( > > FWIW - I'm okay with any PTP patches that are about specific hardware > drivers. When I can, I'll review them for proper use of the core > layer, locking, etc, but at the end of the day, only the people > holding the data sheet know how to talk to the hardware. > > Patches that touch the core layer are another story. These need > careful review by me and other. (Obviously) I was hoping you could cast an eye over the 1-step implementation here. Giving the device a random time reference along the packet looks odd. Unfortunately I don't have much (any?) experience with 1-step myself so I can't trust my own judgment all that much.