| Message ID | 20220805053019.996484-5-nagasuresh.relli@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for Microchip QSPI controller | expand |
On 05/08/2022 07:30, Naga Sureshkumar Relli wrote: > Add the qspi driver to existing Polarfire SoC entry. > > Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- This should be squashed with previous patch. Best regards, Krzysztof
On Fri, Aug 05, 2022 at 08:50:37AM +0200, Krzysztof Kozlowski wrote: > On 05/08/2022 07:30, Naga Sureshkumar Relli wrote: > > Add the qspi driver to existing Polarfire SoC entry. > > > > Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > This should be squashed with previous patch. It's perfectly fine to have a separate patch for MAINTAINERS like this.
On Fri, Aug 05, 2022 at 11:00:19AM +0530, Naga Sureshkumar Relli wrote: > Add the qspi driver to existing Polarfire SoC entry. > +++ b/MAINTAINERS > @@ -17146,6 +17146,7 @@ S: Supported > F: arch/riscv/boot/dts/microchip/ > F: drivers/mailbox/mailbox-mpfs.c > F: drivers/soc/microchip/ > +F: drivers/spi/spi-microchip-core-qspi.c > F: drivers/spi/spi-microchip-core.c > F: include/soc/microchip/mpfs.h You should also add a pattern for the DT binding here.
On 05/08/2022 12:05, Mark Brown wrote: > On Fri, Aug 05, 2022 at 11:00:19AM +0530, Naga Sureshkumar Relli wrote: >> Add the qspi driver to existing Polarfire SoC entry. > >> +++ b/MAINTAINERS >> @@ -17146,6 +17146,7 @@ S: Supported >> F: arch/riscv/boot/dts/microchip/ >> F: drivers/mailbox/mailbox-mpfs.c >> F: drivers/soc/microchip/ >> +F: drivers/spi/spi-microchip-core-qspi.c >> F: drivers/spi/spi-microchip-core.c >> F: include/soc/microchip/mpfs.h > > You should also add a pattern for the DT binding here. All of the bindings for the platform should have entries then right? I'll send a separate patch adding all of the missing bindings. I have a deferred change to the entry that needs to be sent to Arnd anyway so I can queue the two together. Nothing to be gained by waiting until this driver lands in 6.1+ to have MAINTAINERS coverage of the bindings :) Thanks, Conor.
On Fri, Aug 05, 2022 at 12:07:57PM +0000, Conor.Dooley@microchip.com wrote: > On 05/08/2022 12:05, Mark Brown wrote: > >> +++ b/MAINTAINERS > >> @@ -17146,6 +17146,7 @@ S: Supported > >> F: arch/riscv/boot/dts/microchip/ > >> F: drivers/mailbox/mailbox-mpfs.c > >> F: drivers/soc/microchip/ > >> +F: drivers/spi/spi-microchip-core-qspi.c > >> F: drivers/spi/spi-microchip-core.c > >> F: include/soc/microchip/mpfs.h > > You should also add a pattern for the DT binding here. > All of the bindings for the platform should have entries then > right? I'll send a separate patch adding all of the missing > bindings. I have a deferred change to the entry that needs to > be sent to Arnd anyway so I can queue the two together. > Nothing to be gained by waiting until this driver lands in 6.1+ > to have MAINTAINERS coverage of the bindings :) Yes, it's better if everything has coverage - that way the platform maintainers are more likely to see any changes that are needed for the bindings. Sending as part of a bigger patch adding the rest sounds good.
diff --git a/MAINTAINERS b/MAINTAINERS index 295ca16a415b..0329dca23fe2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17146,6 +17146,7 @@ S: Supported F: arch/riscv/boot/dts/microchip/ F: drivers/mailbox/mailbox-mpfs.c F: drivers/soc/microchip/ +F: drivers/spi/spi-microchip-core-qspi.c F: drivers/spi/spi-microchip-core.c F: include/soc/microchip/mpfs.h