| Message ID | 20220811203207.179470-1-mail@conchuod.ie (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: dts: microchip: remove ti,fifo-depth property | expand |
On 11/08/2022 21:32, Conor Dooley wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > From: Conor Dooley <conor.dooley@microchip.com> > > Upgrading dt-schema to v2022.08 brings with it better handling of > unevaluatedProperties, exposing a previously undetected missing > property in the cadence macb dt-binding: > > arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: ethernet@20112000: ethernet-phy@8: Unevaluated properties are not allowed ('ti,fifo-depth' was unexpected) > From schema: Documentation/devicetree/bindings/net/cdns,macb.yaml > > I know what you're thinking, the binding doesn't look to be the problem > and I agree. I am not sure why a TI vendor property was ever actually > added since it has no meaning... just get rid of it. > > Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: bc47b2217f24 ("riscv: dts: microchip: add the sundance polarberry") > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 2 -- > arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 2 -- > 2 files changed, 4 deletions(-) > > diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts > index 044982a11df5..ee548ab61a2a 100644 > --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts > +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts > @@ -84,12 +84,10 @@ &mac1 { > > phy1: ethernet-phy@9 { > reg = <9>; > - ti,fifo-depth = <0x1>; > }; > > phy0: ethernet-phy@8 { > reg = <8>; > - ti,fifo-depth = <0x1>; > }; > }; > > diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts > index 82c93c8f5c17..dc11bb8fc833 100644 > --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts > +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts > @@ -54,12 +54,10 @@ &mac1 { > > phy1: ethernet-phy@5 { > reg = <5>; > - ti,fifo-depth = <0x01>; > }; > > phy0: ethernet-phy@4 { > reg = <4>; > - ti,fifo-depth = <0x01>; > }; > }; > > -- > 2.37.1 >
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index 044982a11df5..ee548ab61a2a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -84,12 +84,10 @@ &mac1 { phy1: ethernet-phy@9 { reg = <9>; - ti,fifo-depth = <0x1>; }; phy0: ethernet-phy@8 { reg = <8>; - ti,fifo-depth = <0x1>; }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts index 82c93c8f5c17..dc11bb8fc833 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -54,12 +54,10 @@ &mac1 { phy1: ethernet-phy@5 { reg = <5>; - ti,fifo-depth = <0x01>; }; phy0: ethernet-phy@4 { reg = <4>; - ti,fifo-depth = <0x01>; }; };