| Message ID | 20220815151451.23293-7-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for Renesas RZ/Five SoC | expand |
On 15/08/2022 16:14, Lad Prabhakar wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Enable the minimal blocks required for booting the Renesas RZ/Five > SMARC EVK with initramfs. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v1->v2 > * New patch > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/renesas/Makefile | 2 ++ > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++ > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++ > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++ > 5 files changed, 73 insertions(+) > create mode 100644 arch/riscv/boot/dts/renesas/Makefile > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi Just to sort out some of my own confusion here - is the smarc EVK shared between your arm boards and the riscv ones? Or just the peripherals etc on the soc? If it is the forver, does the approach suggested here for the allwinner stuff make sense to also use for risc-v stuff with shared parts of devicetrees? https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/ Would at least be interesting in hearing more opinions from the dt people, Geert & Palmer. We have some SOM based stuff too with carriers so I am interested in seeing how the cross platform part of that works out. Thanks, Conor. > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b0ff5fbabb0c 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -3,5 +3,6 @@ subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > subdir-y += microchip > +subdir-y += renesas > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile > new file mode 100644 > index 000000000000..2d3f5751a649 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > new file mode 100644 > index 000000000000..7428f643a9b3 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > @@ -0,0 +1,16 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SMARC EVK > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +/dts-v1/; > + > +#include "r9a07g043.dtsi" > +#include "rzfive-smarc.dtsi" > + > +/ { > + model = "Renesas SMARC EVK based on r9a07g043f01"; > + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043"; > +}; > diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > new file mode 100644 > index 000000000000..4a4acde6a2a7 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SMARC EVK SOM > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +/ { > + chosen { > + bootargs = "ignore_loglevel"; > + }; > + > + memory@48000000 { > + device_type = "memory"; > + /* first 128MB is reserved for secure area. */ > + reg = <0x0 0x48000000 0x0 0x38000000>; > + }; > +}; > + > +&extal_clk { > + clock-frequency = <24000000>; > +}; > diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > new file mode 100644 > index 000000000000..4864a2a62d6b > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > @@ -0,0 +1,32 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SMARC EVK carrier board > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > +#include "rzfive-smarc-som.dtsi" > + > +/ { > + aliases { > + serial0 = &scif0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&pinctrl { > + scif0_pins: scif0 { > + pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */ > + <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */ > + }; > +}; > + > +&scif0 { > + pinctrl-0 = <&scif0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > -- > 2.25.1 >
Hi Conor, On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote: > > On 15/08/2022 16:14, Lad Prabhakar wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Enable the minimal blocks required for booting the Renesas RZ/Five > > SMARC EVK with initramfs. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v1->v2 > > * New patch > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/renesas/Makefile | 2 ++ > > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++ > > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++ > > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++ > > 5 files changed, 73 insertions(+) > > create mode 100644 arch/riscv/boot/dts/renesas/Makefile > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > > Just to sort out some of my own confusion here - is the smarc EVK > shared between your arm boards and the riscv ones? Or just the > peripherals etc on the soc? > RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC SoM and still be used. > If it is the forver, does the approach suggested here for the > allwinner stuff make sense to also use for risc-v stuff with > shared parts of devicetrees? > https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/ > it does make sense. But I wonder where we would place the common shared dtsi that can be used by two arch's. > Would at least be interesting in hearing more opinions from the dt > people, Geert & Palmer. We have some SOM based stuff too with carriers > so I am interested in seeing how the cross platform part of that works > out. > Yep, that would be interesting. Cheers, Prabhakar
On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Enable the minimal blocks required for booting the Renesas RZ/Five > SMARC EVK with initramfs. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Prabhakar, On Mon, Aug 15, 2022 at 10:16 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote: > > On 15/08/2022 16:14, Lad Prabhakar wrote: > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > > > Enable the minimal blocks required for booting the Renesas RZ/Five > > > SMARC EVK with initramfs. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > --- > > > v1->v2 > > > * New patch > > > --- > > > arch/riscv/boot/dts/Makefile | 1 + > > > arch/riscv/boot/dts/renesas/Makefile | 2 ++ > > > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++ > > > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++ > > > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++ > > > 5 files changed, 73 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/renesas/Makefile > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > > > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > > > > Just to sort out some of my own confusion here - is the smarc EVK > > shared between your arm boards and the riscv ones? Or just the > > peripherals etc on the soc? > > > RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL > SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC > SoM and still be used. > > > If it is the forver, does the approach suggested here for the > > allwinner stuff make sense to also use for risc-v stuff with > > shared parts of devicetrees? > > https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/ > > > it does make sense. But I wonder where we would place the common > shared dtsi that can be used by two arch's. You can keep it under arch/arm/boot/dts/renesas/, and refer to it from riscv as <arm64/renesas/...>. Cfr. the symlinks under scripts/dtc/include-prefixes/arm64/ and e.g. cros-ec-keyboard.dtsi. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Fri, Aug 19, 2022 at 9:25 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Aug 15, 2022 at 10:16 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote: > > > On 15/08/2022 16:14, Lad Prabhakar wrote: > > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > > > > > Enable the minimal blocks required for booting the Renesas RZ/Five > > > > SMARC EVK with initramfs. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > --- > > > > v1->v2 > > > > * New patch > > > > --- > > > > arch/riscv/boot/dts/Makefile | 1 + > > > > arch/riscv/boot/dts/renesas/Makefile | 2 ++ > > > > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++ > > > > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++ > > > > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++ > > > > 5 files changed, 73 insertions(+) > > > > create mode 100644 arch/riscv/boot/dts/renesas/Makefile > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > > > > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > > > > > > Just to sort out some of my own confusion here - is the smarc EVK > > > shared between your arm boards and the riscv ones? Or just the > > > peripherals etc on the soc? > > > > > RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL > > SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC > > SoM and still be used. > > > > > If it is the forver, does the approach suggested here for the > > > allwinner stuff make sense to also use for risc-v stuff with > > > shared parts of devicetrees? > > > https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/ > > > > > it does make sense. But I wonder where we would place the common > > shared dtsi that can be used by two arch's. > > You can keep it under arch/arm/boot/dts/renesas/, and refer to > it from riscv as <arm64/renesas/...>. > Cfr. the symlinks under scripts/dtc/include-prefixes/arm64/ and > e.g. cros-ec-keyboard.dtsi. > Thanks for the pointer. Cheers, Prabhakar
On 19/08/2022 12:39, Lad, Prabhakar wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Hi Geert, > > > On Fri, Aug 19, 2022 at 9:25 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: >> >> Hi Prabhakar, >> >> On Mon, Aug 15, 2022 at 10:16 PM Lad, Prabhakar >> <prabhakar.csengg@gmail.com> wrote: >>> On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote: >>>> On 15/08/2022 16:14, Lad Prabhakar wrote: >>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>>>> >>>>> Enable the minimal blocks required for booting the Renesas RZ/Five >>>>> SMARC EVK with initramfs. >>>>> >>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >>>>> --- >>>>> v1->v2 >>>>> * New patch >>>>> --- >>>>> arch/riscv/boot/dts/Makefile | 1 + >>>>> arch/riscv/boot/dts/renesas/Makefile | 2 ++ >>>>> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++ >>>>> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++ >>>>> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++ >>>>> 5 files changed, 73 insertions(+) >>>>> create mode 100644 arch/riscv/boot/dts/renesas/Makefile >>>>> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts >>>>> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi >>>> >>>> Just to sort out some of my own confusion here - is the smarc EVK >>>> shared between your arm boards and the riscv ones? Or just the >>>> peripherals etc on the soc? >>>> >>> RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL >>> SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC >>> SoM and still be used. >>> >>>> If it is the forver, does the approach suggested here for the >>>> allwinner stuff make sense to also use for risc-v stuff with >>>> shared parts of devicetrees? >>>> https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/ >>>> >>> it does make sense. But I wonder where we would place the common >>> shared dtsi that can be used by two arch's. >> >> You can keep it under arch/arm/boot/dts/renesas/, and refer to >> it from riscv as <arm64/renesas/...>. >> Cfr. the symlinks under scripts/dtc/include-prefixes/arm64/ and >> e.g. cros-ec-keyboard.dtsi. >> Is this something that you intend doing or is that future work? I had a quick, and I mean quick, look through the arm smarc dtsi and none of them appeared to be a 1:1 match with what I see here. I assume that's got something to do with the "minimal" in the patch's subject line, and some re-org of the arm files would be required? In any case, you've not introduced any more dtbs_check detectable issues so you're good in my book whichever way you do it. Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b0ff5fbabb0c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -3,5 +3,6 @@ subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip +subdir-y += renesas obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..2d3f5751a649 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts new file mode 100644 index 000000000000..7428f643a9b3 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a07g043.dtsi" +#include "rzfive-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043f01"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043"; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi new file mode 100644 index 000000000000..4a4acde6a2a7 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK SOM + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/ { + chosen { + bootargs = "ignore_loglevel"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi new file mode 100644 index 000000000000..4864a2a62d6b --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK carrier board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> +#include "rzfive-smarc-som.dtsi" + +/ { + aliases { + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pinctrl { + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */ + <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */ + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +};
Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- v1->v2 * New patch --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++ 5 files changed, 73 insertions(+) create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi