diff mbox series

[v2,5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

Message ID 20220815151451.23293-6-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series Add support for Renesas RZ/Five SoC | expand

Commit Message

Prabhakar Aug. 15, 2022, 3:14 p.m. UTC 
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).

Below is the list of IP blocks added in the initial SoC DTSI which can be
used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* Dropped including makefile change
* Updated ndev count
---
 arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
 1 file changed, 121 insertions(+)
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi

Comments

Geert Uytterhoeven Aug. 19, 2022, 8:04 a.m. UTC | #1 
Hi Prabhalar,

On Mon, Aug 15, 2022 at 5:17 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SoC

My first thought was:

    This should be arch/riscv/boot/dts/renesas/r9a07g043f01.dtsi,
     including the common r9a07g043.dtsi, shared by
     arch/arm64/boot/dts/renesas/r9a07g043u11.dtsi.

Then I realized this is harder than it sounds, due:

> +       soc: soc {
> +               compatible = "simple-bus";
> +               interrupt-parent = <&plic>;

vs. "interrupt-parent = <&plic>;" for r9a07g043u11, but mostly
due to

> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               scif0: serial@1004b800 {
> +                       compatible = "renesas,scif-r9a07g043",
> +                                    "renesas,scif-r9a07g044";
> +                       reg = <0 0x1004b800 0 0x400>;
> +                       interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <414 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <415 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <413 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <416 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <416 IRQ_TYPE_LEVEL_HIGH>;

vs. "interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH> ..." on
r9a07g043u11.
Interestingly, the actual hardware interrupt numbers are the same,
but the GIC DT bindings abstracts the offset of 32 by using a second
cell and GIC_SPI.  Unfortunately this cannot be handled by some CPP
magic, as dtc does not support arithmetic operations yet.

I expect this or similar issues to pop up everywhere, when more
RISCV-V SoCs will appear that share the non-CPU parts with ARM SoCs.

Ignoring this issue, which we probably can solve only later:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Lad, Prabhakar Aug. 19, 2022, 11:42 a.m. UTC | #2 
Hi Geert,

On Fri, Aug 19, 2022 at 9:05 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhalar,
>
> On Mon, Aug 15, 2022 at 5:17 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
>
> My first thought was:
>
>     This should be arch/riscv/boot/dts/renesas/r9a07g043f01.dtsi,
>      including the common r9a07g043.dtsi, shared by
>      arch/arm64/boot/dts/renesas/r9a07g043u11.dtsi.
>
> Then I realized this is harder than it sounds, due:
>
Indeed, my initial thought after the comments from Conor was we could
share the SoC dtsi, but that would be to messey due to PLIC.

Cheers,
Prabhakar

> > +       soc: soc {
> > +               compatible = "simple-bus";
> > +               interrupt-parent = <&plic>;
>
> vs. "interrupt-parent = <&plic>;" for r9a07g043u11, but mostly
> due to
>
> > +               #address-cells = <2>;
> > +               #size-cells = <2>;
> > +               ranges;
> > +
> > +               scif0: serial@1004b800 {
> > +                       compatible = "renesas,scif-r9a07g043",
> > +                                    "renesas,scif-r9a07g044";
> > +                       reg = <0 0x1004b800 0 0x400>;
> > +                       interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <414 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <415 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <413 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <416 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <416 IRQ_TYPE_LEVEL_HIGH>;
>
> vs. "interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH> ..." on
> r9a07g043u11.
> Interestingly, the actual hardware interrupt numbers are the same,
> but the GIC DT bindings abstracts the offset of 32 by using a second
> cell and GIC_SPI.  Unfortunately this cannot be handled by some CPP
> magic, as dtc does not support arithmetic operations yet.
>
> I expect this or similar issues to pop up everywhere, when more
> RISCV-V SoCs will appear that share the non-CPU parts with ARM SoCs.
>
> Ignoring this issue, which we probably can solve only later:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Conor Dooley Aug. 19, 2022, 6:40 p.m. UTC | #3 
Hey Prabhakar,
(btw should I use Lad or Prabhakar?)

On 15/08/2022 16:14, Lad Prabhakar wrote:
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
> 
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * Dropped including makefile change
> * Updated ndev count
> ---
>  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>  1 file changed, 121 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> 
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> new file mode 100644
> index 000000000000..b288d2607796
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SoC
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/r9a07g043-cpg.h>
> +
> +/ {
> +	compatible = "renesas,r9a07g043";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> +	extal_clk: extal-clk {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;

What's the value in having the clock-frequency here if the board .dtsi
overwrites it? dtbs_check will complain if someone forgets to fill it
IIUC & what the missing frequency means is also kinda obvious, no?

That aside, by convention so far we have put things like extals or
reference clocks below the /cpus node. Could you do the same here too
please?

> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <24000000>;
> +
> +		ax45mp: cpu@0 {
> +			compatible = "andestech,ax45mp", "riscv";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			status = "okay";
> +			riscv,isa = "rv64imafdc";
> +			mmu-type = "riscv,sv39";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <0x40>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <0x40>;
> +			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> +				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;

I've been on a bit of a topology-fixing binge lately, so I noticed
that you are missing a link to the l2 cache here. FWIW this does show
up in userspace with things like "lstopo" so it might be nice to add
that in from the start. You don't need to have a driver for it at all,
just the entry itself & a "next-level-cache" entry for the CPU.

Other than those two things, and this l2 one is in the "nice to have"
category:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> +
> +			cpu0_intc: interrupt-controller {
> +				#interrupt-cells = <1>;
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +			};
> +		};
> +	};
> +
> +	soc: soc {
> +		compatible = "simple-bus";
> +		interrupt-parent = <&plic>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		scif0: serial@1004b800 {
> +			compatible = "renesas,scif-r9a07g043",
> +				     "renesas,scif-r9a07g044";
> +			reg = <0 0x1004b800 0 0x400>;
> +			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> +				     <414 IRQ_TYPE_LEVEL_HIGH>,
> +				     <415 IRQ_TYPE_LEVEL_HIGH>,
> +				     <413 IRQ_TYPE_LEVEL_HIGH>,
> +				     <416 IRQ_TYPE_LEVEL_HIGH>,
> +				     <416 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "eri", "rxi", "txi",
> +					  "bri", "dri", "tei";
> +			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> +			clock-names = "fck";
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> +			status = "disabled";
> +		};
> +
> +		cpg: clock-controller@11010000 {
> +			compatible = "renesas,r9a07g043-cpg";
> +			reg = <0 0x11010000 0 0x10000>;
> +			clocks = <&extal_clk>;
> +			clock-names = "extal";
> +			#clock-cells = <2>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <0>;
> +		};
> +
> +		sysc: system-controller@11020000 {
> +			compatible = "renesas,r9a07g043-sysc";
> +			reg = <0 0x11020000 0 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		pinctrl: pinctrl@11030000 {
> +			compatible = "renesas,r9a07g043-pinctrl";
> +			reg = <0 0x11030000 0 0x10000>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			#interrupt-cells = <2>;
> +			interrupt-controller;
> +			gpio-ranges = <&pinctrl 0 0 152>;
> +			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_GPIO_RSTN>,
> +				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
> +				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> +		};
> +
> +		plic: interrupt-controller@12c00000 {
> +			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> +			#interrupt-cells = <2>;
> +			#address-cells = <0>;
> +			riscv,ndev = <512>;
> +			interrupt-controller;
> +			reg = <0x0 0x12c00000 0 0x400000>;
> +			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> +			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> +		};
> +	};
> +};
Geert Uytterhoeven Aug. 20, 2022, 8:45 a.m. UTC | #4 
Hi Conor,

On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote:
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * Dropped including makefile change
> > * Updated ndev count
> > ---
> >  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> >  1 file changed, 121 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > new file mode 100644
> > index 000000000000..b288d2607796
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/clock/r9a07g043-cpg.h>
> > +
> > +/ {
> > +     compatible = "renesas,r9a07g043";
> > +     #address-cells = <2>;
> > +     #size-cells = <2>;
> > +
> > +     /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > +     extal_clk: extal-clk {
> > +             compatible = "fixed-clock";
> > +             #clock-cells = <0>;
> > +             /* This value must be overridden by the board */
> > +             clock-frequency = <0>;
>
> What's the value in having the clock-frequency here if the board .dtsi
> overwrites it? dtbs_check will complain if someone forgets to fill it
> IIUC & what the missing frequency means is also kinda obvious, no?

Some external clocks may be optional. Hence "dtbs_check" will complain
if no "clock-frequency" is missing.

>
> That aside, by convention so far we have put things like extals or
> reference clocks below the /cpus node. Could you do the same here too
> please?

Really? We've been putting them at the root node for a long time,
since the separate "clocks" grouping subnode was deprecated.
The extal-clk is not even part of the SoC, so it should definitely
not be under the /cpus node.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Conor Dooley Aug. 20, 2022, 8:49 a.m. UTC | #5 
On 20/08/2022 09:45, Geert Uytterhoeven wrote:
> Hi Conor,
> 
> On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote:
>> On 15/08/2022 16:14, Lad Prabhakar wrote:
>>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
>>> Single).
>>>
>>> Below is the list of IP blocks added in the initial SoC DTSI which can be
>>> used to boot via initramfs on RZ/Five SMARC EVK:
>>> - AX45MP CPU
>>> - CPG
>>> - PINCTRL
>>> - PLIC
>>> - SCIF0
>>> - SYSC
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> v1->v2
>>> * Dropped including makefile change
>>> * Updated ndev count
>>> ---
>>>  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>>>  1 file changed, 121 insertions(+)
>>>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>>>
>>> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>>> new file mode 100644
>>> index 000000000000..b288d2607796
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>>> @@ -0,0 +1,121 @@
>>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +/*
>>> + * Device Tree Source for the RZ/Five SoC
>>> + *
>>> + * Copyright (C) 2022 Renesas Electronics Corp.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/clock/r9a07g043-cpg.h>
>>> +
>>> +/ {
>>> +     compatible = "renesas,r9a07g043";
>>> +     #address-cells = <2>;
>>> +     #size-cells = <2>;
>>> +
>>> +     /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
>>> +     extal_clk: extal-clk {
>>> +             compatible = "fixed-clock";
>>> +             #clock-cells = <0>;
>>> +             /* This value must be overridden by the board */
>>> +             clock-frequency = <0>;
>>
>> What's the value in having the clock-frequency here if the board .dtsi
>> overwrites it? dtbs_check will complain if someone forgets to fill it
>> IIUC & what the missing frequency means is also kinda obvious, no?
> 
> Some external clocks may be optional. Hence "dtbs_check" will complain
> if no "clock-frequency" is missing.

Right, seems reasonable enough.

> 
>>
>> That aside, by convention so far we have put things like extals or
>> reference clocks below the /cpus node. Could you do the same here too
>> please?
> 
> Really? We've been putting them at the root node for a long time,
> since the separate "clocks" grouping subnode was deprecated.
> The extal-clk is not even part of the SoC, so it should definitely
> not be under the /cpus node.

Under may have been a confusing choice of words, I meant "physically"
under it in the file. Maybe after would have been a better choice of
words? I wasn't suggesting you put it inside the CPUs node.
Does that make more sense?
Conor.
Geert Uytterhoeven Aug. 20, 2022, 12:07 p.m. UTC | #6 
Hi Conor,

On Sat, Aug 20, 2022 at 10:49 AM <Conor.Dooley@microchip.com> wrote:
> On 20/08/2022 09:45, Geert Uytterhoeven wrote:
> > On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote:
> >> On 15/08/2022 16:14, Lad Prabhakar wrote:
> >>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> >>> Single).
> >>>
> >>> Below is the list of IP blocks added in the initial SoC DTSI which can be
> >>> used to boot via initramfs on RZ/Five SMARC EVK:
> >>> - AX45MP CPU
> >>> - CPG
> >>> - PINCTRL
> >>> - PLIC
> >>> - SCIF0
> >>> - SYSC
> >>>
> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> >> That aside, by convention so far we have put things like extals or
> >> reference clocks below the /cpus node. Could you do the same here too
> >> please?
> >
> > Really? We've been putting them at the root node for a long time,
> > since the separate "clocks" grouping subnode was deprecated.
> > The extal-clk is not even part of the SoC, so it should definitely
> > not be under the /cpus node.
>
> Under may have been a confusing choice of words, I meant "physically"
> under it in the file. Maybe after would have been a better choice of
> words? I wasn't suggesting you put it inside the CPUs node.
> Does that make more sense?

Oh right, you mean the order of the nodes. Yes, "extal-clk" should
be after "cpus", following alphabetical sort order, as the nodes have no
unit addresses.

Sorry for missing that in my review.  I also misread "below"
(in Dutch there is only a single word for "below" and "under" ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
new file mode 100644
index 000000000000..b288d2607796
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
@@ -0,0 +1,121 @@ 
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/r9a07g043-cpg.h>
+
+/ {
+	compatible = "renesas,r9a07g043";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+	extal_clk: extal-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <24000000>;
+
+		ax45mp: cpu@0 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
+				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		scif0: serial@1004b800 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004b800 0 0x400>;
+			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+				     <414 IRQ_TYPE_LEVEL_HIGH>,
+				     <415 IRQ_TYPE_LEVEL_HIGH>,
+				     <413 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller@11010000 {
+			compatible = "renesas,r9a07g043-cpg";
+			reg = <0 0x11010000 0 0x10000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sysc: system-controller@11020000 {
+			compatible = "renesas,r9a07g043-sysc";
+			reg = <0 0x11020000 0 0x10000>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl@11030000 {
+			compatible = "renesas,r9a07g043-pinctrl";
+			reg = <0 0x11030000 0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			gpio-ranges = <&pinctrl 0 0 152>;
+			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_GPIO_RSTN>,
+				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
+				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+		};
+
+		plic: interrupt-controller@12c00000 {
+			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			riscv,ndev = <512>;
+			interrupt-controller;
+			reg = <0x0 0x12c00000 0 0x400000>;
+			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+		};
+	};
+};