| Message ID | 20220817204357.21753-2-leoyang.li@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ls208xa dts updates | expand |
On Wed, Aug 17, 2022 at 03:43:52PM -0500, Li Yang wrote: > Add mmio mdio mux nodes from the on-board FPGA. > > Signed-off-by: Li Yang <leoyang.li@nxp.com> > --- > .../boot/dts/freescale/fsl-ls2080a-qds.dts | 69 +++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts > index f6c3ee78ace0..ef79c9a78f89 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts > @@ -23,3 +23,72 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > }; > + > +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ > +&dpmac9 { > + phy-handle = <&mdio0_phy12>; > + phy-connection-type = "sgmii"; > +}; > + > +&dpmac10 { > + phy-handle = <&mdio0_phy13>; > + phy-connection-type = "sgmii"; > +}; > + > +&dpmac11 { > + phy-handle = <&mdio0_phy14>; > + phy-connection-type = "sgmii"; > +}; > + > +&dpmac12 { > + phy-handle = <&mdio0_phy15>; > + phy-connection-type = "sgmii"; > +}; > + > +&ifc { > + boardctrl: board-control@3,0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-mfd"; > + reg = <3 0 0x300>; > + ranges = <0 3 0 0x300>; > + > + mdio-mux-emi1@54 { > + compatible = "mdio-mux-mmioreg", "mdio-mux"; > + mdio-parent-bus = <&emdio1>; > + reg = <0x54 1>; /* BRDCFG4 */ > + mux-mask = <0xe0>; /* EMI1_MDIO */ > + Unnecessary newline. > + #address-cells=<1>; > + #size-cells = <0>; > + > + /* Child MDIO buses, one for each riser card: > + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. > + * VSC8234 PHYs on the riser cards. > + */ > + > + mdio_mux3: mdio@60 { > + reg = <0x60>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + mdio0_phy12: mdio_phy0@1c { Hyphen is recommended in node name. Shawn > + reg = <0x1c>; > + }; > + > + mdio0_phy13: mdio_phy1@1d { > + reg = <0x1d>; > + }; > + > + mdio0_phy14: mdio_phy2@1e { > + reg = <0x1e>; > + }; > + > + mdio0_phy15: mdio_phy3@1f { > + reg = <0x1f>; > + }; > + }; > + }; > + }; > +}; > + > -- > 2.37.1 >
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts index f6c3ee78ace0..ef79c9a78f89 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts @@ -23,3 +23,72 @@ chosen { stdout-path = "serial0:115200n8"; }; }; + +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ +&dpmac9 { + phy-handle = <&mdio0_phy12>; + phy-connection-type = "sgmii"; +}; + +&dpmac10 { + phy-handle = <&mdio0_phy13>; + phy-connection-type = "sgmii"; +}; + +&dpmac11 { + phy-handle = <&mdio0_phy14>; + phy-connection-type = "sgmii"; +}; + +&dpmac12 { + phy-handle = <&mdio0_phy15>; + phy-connection-type = "sgmii"; +}; + +&ifc { + boardctrl: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-mfd"; + reg = <3 0 0x300>; + ranges = <0 3 0 0x300>; + + mdio-mux-emi1@54 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&emdio1>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1_MDIO */ + + #address-cells=<1>; + #size-cells = <0>; + + /* Child MDIO buses, one for each riser card: + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. + * VSC8234 PHYs on the riser cards. + */ + + mdio_mux3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + mdio0_phy12: mdio_phy0@1c { + reg = <0x1c>; + }; + + mdio0_phy13: mdio_phy1@1d { + reg = <0x1d>; + }; + + mdio0_phy14: mdio_phy2@1e { + reg = <0x1e>; + }; + + mdio0_phy15: mdio_phy3@1f { + reg = <0x1f>; + }; + }; + }; + }; +}; +
Add mmio mdio mux nodes from the on-board FPGA. Signed-off-by: Li Yang <leoyang.li@nxp.com> --- .../boot/dts/freescale/fsl-ls2080a-qds.dts | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+)