diff mbox series

[net-next,09/14] ptp: mlx5: convert to .adjfine and adjust_by_scaled_ppm

Message ID 20220818222742.1070935-10-jacob.e.keller@intel.com (mailing list archive)
State Changes Requested
Delegated to: Netdev Maintainers
Headers show
Series ptp: convert drivers to .adjfine | expand

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Commit Message

Jacob Keller Aug. 18, 2022, 10:27 p.m. UTC
The mlx5 implementation of .adjfreq is implemented in terms of a
straight forward "base * ppb / 1 billion" calculation.

Convert this to the .adjfine interface and use adjust_by_scaled_ppm for the
calculation  of the new mult value.

Note that the mlx5_ptp_adjfreq_real_time function expects input in terms of
ppb, so use the scaled_ppm_to_ppb to convert before passing to this
function.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Cc: Saeed Mahameed <saeedm@nvidia.com>
Cc: Leon Romanovsky <leon@kernel.org>
Cc: Aya Levin <ayal@nvidia.com>
---

I do not have this hardware, and have only compile tested the change.

 .../ethernet/mellanox/mlx5/core/lib/clock.c   | 22 +++++--------------
 1 file changed, 6 insertions(+), 16 deletions(-)

Comments

Gal Pressman Aug. 23, 2022, 3:30 p.m. UTC | #1
On 19/08/2022 01:27, Jacob Keller wrote:
> The mlx5 implementation of .adjfreq is implemented in terms of a
> straight forward "base * ppb / 1 billion" calculation.
>
> Convert this to the .adjfine interface and use adjust_by_scaled_ppm for the
> calculation  of the new mult value.
>
> Note that the mlx5_ptp_adjfreq_real_time function expects input in terms of
> ppb, so use the scaled_ppm_to_ppb to convert before passing to this
> function.
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Cc: Saeed Mahameed <saeedm@nvidia.com>
> Cc: Leon Romanovsky <leon@kernel.org>
> Cc: Aya Levin <ayal@nvidia.com>
> ---
>
> I do not have this hardware, and have only compile tested the change.
>
>  .../ethernet/mellanox/mlx5/core/lib/clock.c   | 22 +++++--------------
>  1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> index 91e806c1aa21..34871ab659d9 100644
> --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> @@ -330,35 +330,25 @@ static int mlx5_ptp_adjfreq_real_time(struct mlx5_core_dev *mdev, s32 freq)
>  	return mlx5_set_mtutc(mdev, in, sizeof(in));
>  }
>  
> -static int mlx5_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
> +static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long delta)

Small nit, please rename delta to scaled_ppm.
I'll try to get this tested in our regression soon.
Gal Pressman Aug. 25, 2022, 6:31 a.m. UTC | #2
On 23/08/2022 18:30, Gal Pressman wrote:
> On 19/08/2022 01:27, Jacob Keller wrote:
>> The mlx5 implementation of .adjfreq is implemented in terms of a
>> straight forward "base * ppb / 1 billion" calculation.
>>
>> Convert this to the .adjfine interface and use adjust_by_scaled_ppm for the
>> calculation  of the new mult value.
>>
>> Note that the mlx5_ptp_adjfreq_real_time function expects input in terms of
>> ppb, so use the scaled_ppm_to_ppb to convert before passing to this
>> function.
>>
>> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
>> Cc: Saeed Mahameed <saeedm@nvidia.com>
>> Cc: Leon Romanovsky <leon@kernel.org>
>> Cc: Aya Levin <ayal@nvidia.com>
>> ---
>>
>> I do not have this hardware, and have only compile tested the change.
>>
>>  .../ethernet/mellanox/mlx5/core/lib/clock.c   | 22 +++++--------------
>>  1 file changed, 6 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
>> index 91e806c1aa21..34871ab659d9 100644
>> --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
>> +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
>> @@ -330,35 +330,25 @@ static int mlx5_ptp_adjfreq_real_time(struct mlx5_core_dev *mdev, s32 freq)
>>  	return mlx5_set_mtutc(mdev, in, sizeof(in));
>>  }
>>  
>> -static int mlx5_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
>> +static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long delta)
> Small nit, please rename delta to scaled_ppm.
> I'll try to get this tested in our regression soon.

Tested-by: Shirly Ohnona <shirlyo@nvidia.com>
Jacob Keller Aug. 25, 2022, 9:59 p.m. UTC | #3
> -----Original Message-----
> From: Gal Pressman <gal@nvidia.com>
> Sent: Tuesday, August 23, 2022 8:31 AM
> To: Keller, Jacob E <jacob.e.keller@intel.com>; netdev@vger.kernel.org
> Cc: K. Y. Srinivasan <kys@microsoft.com>; Haiyang Zhang
> <haiyangz@microsoft.com>; Stephen Hemminger <sthemmin@microsoft.com>;
> Wei Liu <wei.liu@kernel.org>; Cui, Dexuan <decui@microsoft.com>; Tom
> Lendacky <thomas.lendacky@amd.com>; Shyam Sundar S K <Shyam-sundar.S-
> k@amd.com>; David S. Miller <davem@davemloft.net>; Eric Dumazet
> <edumazet@google.com>; Jakub Kicinski <kuba@kernel.org>; Paolo Abeni
> <pabeni@redhat.com>; Siva Reddy Kallam <siva.kallam@broadcom.com>;
> Prashant Sreedharan <prashant@broadcom.com>; Michael Chan
> <mchan@broadcom.com>; Yisen Zhuang <yisen.zhuang@huawei.com>; Salil
> Mehta <salil.mehta@huawei.com>; Brandeburg, Jesse
> <jesse.brandeburg@intel.com>; Nguyen, Anthony L
> <anthony.l.nguyen@intel.com>; Tariq Toukan <tariqt@nvidia.com>; Saeed
> Mahameed <saeedm@nvidia.com>; Leon Romanovsky <leon@kernel.org>;
> Bryan Whitehead <bryan.whitehead@microchip.com>; Sergey Shtylyov
> <s.shtylyov@omp.ru>; Giuseppe Cavallaro <peppe.cavallaro@st.com>;
> Alexandre Torgue <alexandre.torgue@foss.st.com>; Jose Abreu
> <joabreu@synopsys.com>; Maxime Coquelin <mcoquelin.stm32@gmail.com>;
> Richard Cochran <richardcochran@gmail.com>; Thampi, Vivek
> <vithampi@vmware.com>; VMware PV-Drivers Reviewers <pv-
> drivers@vmware.com>; Jie Wang <wangjie125@huawei.com>; Guangbin Huang
> <huangguangbin2@huawei.com>; Eran Ben Elisha <eranbe@nvidia.com>; Aya
> Levin <ayal@nvidia.com>; Cai Huoqing <cai.huoqing@linux.dev>; Biju Das
> <biju.das.jz@bp.renesas.com>; Lad Prabhakar <prabhakar.mahadev-
> lad.rj@bp.renesas.com>; Phil Edworthy <phil.edworthy@renesas.com>; Jiasheng
> Jiang <jiasheng@iscas.ac.cn>; Gustavo A. R. Silva <gustavoars@kernel.org>; Linus
> Walleij <linus.walleij@linaro.org>; Wan Jiabing <wanjiabing@vivo.com>; Lv Ruyi
> <lv.ruyi@zte.com.cn>; Arnd Bergmann <arnd@arndb.de>
> Subject: Re: [net-next 09/14] ptp: mlx5: convert to .adjfine and
> adjust_by_scaled_ppm
> 
> On 19/08/2022 01:27, Jacob Keller wrote:
> > The mlx5 implementation of .adjfreq is implemented in terms of a
> > straight forward "base * ppb / 1 billion" calculation.
> >
> > Convert this to the .adjfine interface and use adjust_by_scaled_ppm for the
> > calculation  of the new mult value.
> >
> > Note that the mlx5_ptp_adjfreq_real_time function expects input in terms of
> > ppb, so use the scaled_ppm_to_ppb to convert before passing to this
> > function.
> >
> > Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> > Cc: Saeed Mahameed <saeedm@nvidia.com>
> > Cc: Leon Romanovsky <leon@kernel.org>
> > Cc: Aya Levin <ayal@nvidia.com>
> > ---
> >
> > I do not have this hardware, and have only compile tested the change.
> >
> >  .../ethernet/mellanox/mlx5/core/lib/clock.c   | 22 +++++--------------
> >  1 file changed, 6 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> > index 91e806c1aa21..34871ab659d9 100644
> > --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> > +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> > @@ -330,35 +330,25 @@ static int mlx5_ptp_adjfreq_real_time(struct
> mlx5_core_dev *mdev, s32 freq)
> >  	return mlx5_set_mtutc(mdev, in, sizeof(in));
> >  }
> >
> > -static int mlx5_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
> > +static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long delta)
> 
> Small nit, please rename delta to scaled_ppm.
> I'll try to get this tested in our regression soon.

Will fix that in v2. Thanks for testing!
diff mbox series

Patch

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
index 91e806c1aa21..34871ab659d9 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
@@ -330,35 +330,25 @@  static int mlx5_ptp_adjfreq_real_time(struct mlx5_core_dev *mdev, s32 freq)
 	return mlx5_set_mtutc(mdev, in, sizeof(in));
 }
 
-static int mlx5_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
+static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long delta)
 {
 	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
 	struct mlx5_timer *timer = &clock->timer;
 	struct mlx5_core_dev *mdev;
 	unsigned long flags;
-	int neg_adj = 0;
-	u32 diff;
-	u64 adj;
+	u32 mult;
 	int err;
 
 	mdev = container_of(clock, struct mlx5_core_dev, clock);
-	err = mlx5_ptp_adjfreq_real_time(mdev, delta);
+	err = mlx5_ptp_adjfreq_real_time(mdev, scaled_ppm_to_ppb(delta));
 	if (err)
 		return err;
 
-	if (delta < 0) {
-		neg_adj = 1;
-		delta = -delta;
-	}
-
-	adj = timer->nominal_c_mult;
-	adj *= delta;
-	diff = div_u64(adj, 1000000000ULL);
+	mult = (u32)adjust_by_scaled_ppm(timer->nominal_c_mult, delta);
 
 	write_seqlock_irqsave(&clock->lock, flags);
 	timecounter_read(&timer->tc);
-	timer->cycles.mult = neg_adj ? timer->nominal_c_mult - diff :
-				       timer->nominal_c_mult + diff;
+	timer->cycles.mult = mult;
 	mlx5_update_clock_info_page(mdev);
 	write_sequnlock_irqrestore(&clock->lock, flags);
 
@@ -605,7 +595,7 @@  static const struct ptp_clock_info mlx5_ptp_clock_info = {
 	.n_per_out	= 0,
 	.n_pins		= 0,
 	.pps		= 0,
-	.adjfreq	= mlx5_ptp_adjfreq,
+	.adjfine	= mlx5_ptp_adjfine,
 	.adjtime	= mlx5_ptp_adjtime,
 	.gettimex64	= mlx5_ptp_gettimex,
 	.settime64	= mlx5_ptp_settime,