[v3,1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support

Commit Message

Richard Zhu Aug. 18, 2022, 7:02 a.m. UTC

On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3)
of SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.

And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add the i.MX8MP PCIe PHY PERST support here.

Signed-off-by: Richard Zhu <[e-mail]>
---
 drivers/reset/reset-imx7.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Philipp Zabel Aug. 18, 2022, 8:50 a.m. UTC | #1

Hi Richard,

On Do, 2022-08-18 at 15:02 +0800, Richard Zhu wrote:
> On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3)
> of SRC_PCIEPHY_RCR is 1b'1.
> But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> 
> And the PERST bit should be kept 1b'1 after power and clocks are stable.
> So add the i.MX8MP PCIe PHY PERST support here.

the description is good now. It would be nice if this could also be
mentioned in the Reference Manual.

Please replace "add" with "fix" in the subject, as I requested earlier:
"reset: imx7: Fix i.MX8MP PCIe PHY PERST support".

And add a fixes line:

Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")

With those two changes,
Reviewed-by: Philipp Zabel <[e-mail]>

regards
Philipp

Richard Zhu Aug. 18, 2022, 10:53 a.m. UTC | #2

> -----Original Message-----
> From: Philipp Zabel <[e-mail]>
> Sent: 2022年8月18日 16:51
> To: Hongxing Zhu <[e-mail]>; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]
> Cc: [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]; dl-linux-imx
> <[e-mail]>
> Subject: Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST
> support
> 
> Hi Richard,
> 
> On Do, 2022-08-18 at 15:02 +0800, Richard Zhu wrote:
> > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST
> > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1.
> > But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> >
> > And the PERST bit should be kept 1b'1 after power and clocks are stable.
> > So add the i.MX8MP PCIe PHY PERST support here.
> 
> the description is good now. It would be nice if this could also be mentioned in
> the Reference Manual.
> 
> Please replace "add" with "fix" in the subject, as I requested earlier:
> "reset: imx7: Fix i.MX8MP PCIe PHY PERST support".
> 
> And add a fixes line:
> 
> Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> 
> With those two changes,
> Reviewed-by: Philipp Zabel <[e-mail]>
> 
Hi Philipp:
Okay, would be changed in next version.
Thanks for your review.

Best Regards
Richard Zhu

> regards
> Philipp

Lorenzo Pieralisi Aug. 29, 2022, 8:10 a.m. UTC | #3

On Thu, Aug 18, 2022 at 10:53:24AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Philipp Zabel <[e-mail]>
> > Sent: 2022年8月18日 16:51
> > To: Hongxing Zhu <[e-mail]>; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]
> > Cc: [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; dl-linux-imx
> > <[e-mail]>
> > Subject: Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST
> > support
> > 
> > Hi Richard,
> > 
> > On Do, 2022-08-18 at 15:02 +0800, Richard Zhu wrote:
> > > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST
> > > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1.
> > > But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> > >
> > > And the PERST bit should be kept 1b'1 after power and clocks are stable.
> > > So add the i.MX8MP PCIe PHY PERST support here.
> > 
> > the description is good now. It would be nice if this could also be mentioned in
> > the Reference Manual.
> > 
> > Please replace "add" with "fix" in the subject, as I requested earlier:
> > "reset: imx7: Fix i.MX8MP PCIe PHY PERST support".
> > 
> > And add a fixes line:
> > 
> > Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> > 
> > With those two changes,
> > Reviewed-by: Philipp Zabel <[e-mail]>
> > 
> Hi Philipp:
> Okay, would be changed in next version.

AFAICS there is still a pending comment on patch (2) but I will
mark this as "Changes requested" and wait for the next version.

Lorenzo

> Thanks for your review.
> 
> Best Regards
> Richard Zhu
> 
> > regards
> > Philipp
> _______________________________________________
> linux-arm-kernel mailing list
> [e-mail]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Richard Zhu Aug. 29, 2022, 8:14 a.m. UTC | #4

> -----Original Message-----
> From: Lorenzo Pieralisi <[e-mail]>
> Sent: 2022年8月29日 16:10
> To: Hongxing Zhu <[e-mail]>
> Cc: Philipp Zabel <[e-mail]>; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]; dl-linux-imx
> <[e-mail]>
> Subject: Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST
> support
> 
> On Thu, Aug 18, 2022 at 10:53:24AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Philipp Zabel <[e-mail]>
> > > Sent: 2022年8月18日 16:51
> > > To: Hongxing Zhu <[e-mail]>; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]
> > > Cc: [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; dl-linux-imx
> > > <[e-mail]>
> > > Subject: Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY
> > > PERST support
> > >
> > > Hi Richard,
> > >
> > > On Do, 2022-08-18 at 15:02 +0800, Richard Zhu wrote:
> > > > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST
> > > > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1.
> > > > But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> > > >
> > > > And the PERST bit should be kept 1b'1 after power and clocks are stable.
> > > > So add the i.MX8MP PCIe PHY PERST support here.
> > >
> > > the description is good now. It would be nice if this could also be
> > > mentioned in the Reference Manual.
> > >
> > > Please replace "add" with "fix" in the subject, as I requested earlier:
> > > "reset: imx7: Fix i.MX8MP PCIe PHY PERST support".
> > >
> > > And add a fixes line:
> > >
> > > Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> > >
> > > With those two changes,
> > > Reviewed-by: Philipp Zabel <[e-mail]>
> > >
> > Hi Philipp:
> > Okay, would be changed in next version.
> 
> AFAICS there is still a pending comment on patch (2) but I will mark this as
> "Changes requested" and wait for the next version.
> 
Hi Lorenzo:
Thanks for your kindly help.
I had prepared the v4 version. And I also pinged Lucas privately and hope
 he can take a look at it. Thus, I can add his ack in v4 series.

Anyway, I would issue the v4 series tomorrow.
Best Regards
Richard Zhu

> Lorenzo
> 
> > Thanks for your review.
> >
> > Best Regards
> > Richard Zhu
> >
> > > regards
> > > Philipp
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [e-mail]
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists
> > .infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=05%7
> C0
> >
> 1%7Chongxing.zhu%40nxp.com%7Cd0470ce757e64e6e7c6a08da8995e689%
> 7C686ea1
> >
> d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637973574166682920%7CUnk
> nown%7CTW
> >
> FpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXV
> CI6
> >
> Mn0%3D%7C3000%7C%7C%7C&amp;sdata=LE4i5OQ03XV0tUo%2FWIm8L9m
> Nx7ZNZMUhfpo
> > Lji4%2BDRM%3D&amp;reserved=0

Patch

diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 185a333df66c..d2408725eb2c 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -329,6 +329,7 @@  static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
 		break;
 
 	case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+	case IMX8MP_RESET_PCIEPHY_PERST:
 		value = assert ? 0 : bit;
 		break;
 	}