diff mbox series

[8/8] drm/i915/mtl: Hook up interrupts for standalone media

Message ID 20220829170238.969875-9-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series i915: Add "standalone media" support for MTL | expand

Commit Message

Matt Roper Aug. 29, 2022, 5:02 p.m. UTC 
Top-level handling of standalone media interrupts will be processed as
part of the primary GT's interrupt handler (since primary and media GTs
share an MMIO space, unlike remote tile setups).  When we get down to
the point of handling engine interrupts, we need to take care to lookup
VCS and VECS engines in the media GT rather than the primary.

There are also a couple of additional "other" instance bits that
correspond to the media GT's GuC and media GT's power management
interrupts; we need to direct those to the media GT instance as well.

Bspec: 45605
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_irq.c   | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 ++
 drivers/gpu/drm/i915/gt/intel_sa_media.c |  7 +++++++
 drivers/gpu/drm/i915/i915_drv.h          |  3 +++
 4 files changed, 31 insertions(+)

Comments

Daniele Ceraolo Spurio Sept. 1, 2022, 11:42 p.m. UTC | #1 
On 8/29/2022 10:02 AM, Matt Roper wrote:
> Top-level handling of standalone media interrupts will be processed as
> part of the primary GT's interrupt handler (since primary and media GTs
> share an MMIO space, unlike remote tile setups).  When we get down to
> the point of handling engine interrupts, we need to take care to lookup
> VCS and VECS engines in the media GT rather than the primary.
>
> There are also a couple of additional "other" instance bits that
> correspond to the media GT's GuC and media GT's power management
> interrupts; we need to direct those to the media GT instance as well.
>
> Bspec: 45605
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/i915/gt/intel_gt_irq.c   | 19 +++++++++++++++++++
>   drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 ++
>   drivers/gpu/drm/i915/gt/intel_sa_media.c |  7 +++++++
>   drivers/gpu/drm/i915/i915_drv.h          |  3 +++
>   4 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 0dfd0c42d00d..f26882fdc24c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -59,11 +59,17 @@ static void
>   gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
>   			const u16 iir)
>   {
> +	struct intel_gt *media_gt = gt->i915->media_gt;
> +
>   	if (instance == OTHER_GUC_INSTANCE)
>   		return guc_irq_handler(&gt->uc.guc, iir);
> +	if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt)
> +		return guc_irq_handler(&media_gt->uc.guc, iir);
>   
>   	if (instance == OTHER_GTPM_INSTANCE)
>   		return gen11_rps_irq_handler(&gt->rps, iir);
> +	if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt)
> +		return gen11_rps_irq_handler(&media_gt->rps, iir);
>   
>   	if (instance == OTHER_KCR_INSTANCE)
>   		return intel_pxp_irq_handler(&gt->pxp, iir);
> @@ -81,6 +87,18 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
>   {
>   	struct intel_engine_cs *engine;
>   
> +	/*
> +	 * Platforms with standalone media have their media engines in another
> +	 * GT.
> +	 */
> +	if (MEDIA_VER(gt->i915) >= 13 &&
> +	    (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
> +		if (!gt->i915->media_gt)
> +			goto err;
> +
> +		gt = gt->i915->media_gt;
> +	}
> +
>   	if (instance <= MAX_ENGINE_INSTANCE)
>   		engine = gt->engine_class[class][instance];
>   	else
> @@ -89,6 +107,7 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
>   	if (likely(engine))
>   		return intel_engine_cs_irq(engine, iir);
>   
> +err:
>   	WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
>   		  class, instance);
>   }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 05a40ef33258..21c7a225157f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1552,6 +1552,8 @@
>   #define   OTHER_GTPM_INSTANCE			1
>   #define   OTHER_KCR_INSTANCE			4
>   #define   OTHER_GSC_INSTANCE			6
> +#define   OTHER_MEDIA_GUC_INSTANCE		16
> +#define   OTHER_MEDIA_GTPM_INSTANCE		17
>   
>   #define GEN11_IIR_REG_SELECTOR(x)		_MMIO(0x190070 + ((x) * 4))
>   
> diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> index cf3053710bbf..41c270f103cf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sa_media.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> @@ -36,5 +36,12 @@ int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
>   	gt->uncore = uncore;
>   	gt->phys_addr = phys_addr;
>   
> +	/*
> +	 * For current platforms we can assume there's only a single
> +	 * media GT and cache it for quick lookup.
> +	 */
> +	drm_WARN_ON(&i915->drm, i915->media_gt);
> +	i915->media_gt = gt;
> +
>   	return 0;
>   }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d45dca70bfa6..917958d42805 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -497,6 +497,9 @@ struct drm_i915_private {
>   
>   	struct kobject *sysfs_gt;
>   
> +	/* Quick lookup of media GT (current platforms only have one) */
> +	struct intel_gt *media_gt;
> +
>   	struct {
>   		struct i915_gem_contexts {
>   			spinlock_t lock; /* locks list */
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 0dfd0c42d00d..f26882fdc24c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -59,11 +59,17 @@  static void
 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
 			const u16 iir)
 {
+	struct intel_gt *media_gt = gt->i915->media_gt;
+
 	if (instance == OTHER_GUC_INSTANCE)
 		return guc_irq_handler(&gt->uc.guc, iir);
+	if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt)
+		return guc_irq_handler(&media_gt->uc.guc, iir);
 
 	if (instance == OTHER_GTPM_INSTANCE)
 		return gen11_rps_irq_handler(&gt->rps, iir);
+	if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt)
+		return gen11_rps_irq_handler(&media_gt->rps, iir);
 
 	if (instance == OTHER_KCR_INSTANCE)
 		return intel_pxp_irq_handler(&gt->pxp, iir);
@@ -81,6 +87,18 @@  gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
 {
 	struct intel_engine_cs *engine;
 
+	/*
+	 * Platforms with standalone media have their media engines in another
+	 * GT.
+	 */
+	if (MEDIA_VER(gt->i915) >= 13 &&
+	    (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
+		if (!gt->i915->media_gt)
+			goto err;
+
+		gt = gt->i915->media_gt;
+	}
+
 	if (instance <= MAX_ENGINE_INSTANCE)
 		engine = gt->engine_class[class][instance];
 	else
@@ -89,6 +107,7 @@  gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
 	if (likely(engine))
 		return intel_engine_cs_irq(engine, iir);
 
+err:
 	WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
 		  class, instance);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 05a40ef33258..21c7a225157f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1552,6 +1552,8 @@ 
 #define   OTHER_GTPM_INSTANCE			1
 #define   OTHER_KCR_INSTANCE			4
 #define   OTHER_GSC_INSTANCE			6
+#define   OTHER_MEDIA_GUC_INSTANCE		16
+#define   OTHER_MEDIA_GTPM_INSTANCE		17
 
 #define GEN11_IIR_REG_SELECTOR(x)		_MMIO(0x190070 + ((x) * 4))
 
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c
index cf3053710bbf..41c270f103cf 100644
--- a/drivers/gpu/drm/i915/gt/intel_sa_media.c
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -36,5 +36,12 @@  int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
 	gt->uncore = uncore;
 	gt->phys_addr = phys_addr;
 
+	/*
+	 * For current platforms we can assume there's only a single
+	 * media GT and cache it for quick lookup.
+	 */
+	drm_WARN_ON(&i915->drm, i915->media_gt);
+	i915->media_gt = gt;
+
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d45dca70bfa6..917958d42805 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -497,6 +497,9 @@  struct drm_i915_private {
 
 	struct kobject *sysfs_gt;
 
+	/* Quick lookup of media GT (current platforms only have one) */
+	struct intel_gt *media_gt;
+
 	struct {
 		struct i915_gem_contexts {
 			spinlock_t lock; /* locks list */