| Message ID | 20220901131756.26060-9-victor.colombo@eldorado.org.br (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Multiple ppc instructions fixes | expand |
On 9/1/22 10:17, Víctor Colombo wrote: > Fix xscvsdqp incorrectly not clearing the FI bit. > Power ISA states that xscvsdqp should always set FPSCR.FI=0 > Right now, QEMU sometimes is incorrectly setting the flag to 1. > > Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> > --- Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> > target/ppc/fpu_helper.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c > index da79c64eca..94029883c7 100644 > --- a/target/ppc/fpu_helper.c > +++ b/target/ppc/fpu_helper.c > @@ -3126,6 +3126,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ > { \ > ppc_vsr_t t = *xt; \ > \ > + helper_reset_fpstatus(env); \ > t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \ > helper_compute_fprf_##ttp(env, t.tfld); \ > \
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index da79c64eca..94029883c7 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3126,6 +3126,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ { \ ppc_vsr_t t = *xt; \ \ + helper_reset_fpstatus(env); \ t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \ helper_compute_fprf_##ttp(env, t.tfld); \ \
Fix xscvsdqp incorrectly not clearing the FI bit. Power ISA states that xscvsdqp should always set FPSCR.FI=0 Right now, QEMU sometimes is incorrectly setting the flag to 1. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> --- target/ppc/fpu_helper.c | 1 + 1 file changed, 1 insertion(+)