| Message ID | 20220906062657.924852-1-ajones@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V: Clean up the Zicbom block size probing | expand |
On Tue, Sep 06, 2022 at 08:26:57AM +0200, Andrew Jones wrote: > From: Palmer Dabbelt <palmer@rivosinc.com> > > This fixes two issues: I truncated the warning's hart ID when porting to > the 64-bit hart ID code, and the original code's warning handling could > fire on an uninitialized hart ID. > > The biggest change here is that riscv_cbom_block_size is no longer > initialized, as IMO the default isn't sane: there's nothing in the ISA > that mandates any specific cache block size, so falling back to one will > just silently produce the wrong answer on some systems. This also > changes the probing order so the cache block size is known before > enabling Zicbom support. > > Fixes: 3aefb2ee5bdd ("riscv: implement Zicbom-based CMO instructions + the t-head variant") > Fixes: 1631ba1259d6 ("riscv: Add support for non-coherent devices using zicbom extension") > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > [Applied Conor Dooley's and Heiko Stuebner's changes.] > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> > --- > arch/riscv/errata/thead/errata.c | 1 + > arch/riscv/kernel/setup.c | 2 +- > arch/riscv/mm/dma-noncoherent.c | 23 +++++++++++++---------- > 3 files changed, 15 insertions(+), 11 deletions(-) > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c > index 202c83f677b2..96648c176f37 100644 > --- a/arch/riscv/errata/thead/errata.c > +++ b/arch/riscv/errata/thead/errata.c > @@ -37,6 +37,7 @@ static bool errata_probe_cmo(unsigned int stage, > if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) > return false; > > + riscv_cbom_block_size = L1_CACHE_BYTES; Darn, of course this doesn't compile independently of Anup's move change. I should have done the move first as Heiko suggested. I'll try again by posting both Anup's move change and this patch rebased on Anup's. Thanks, drew > riscv_noncoherent_supported(); > return true; > #else > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c > index 95ef6e2bf45c..2dfc463b86bb 100644 > --- a/arch/riscv/kernel/setup.c > +++ b/arch/riscv/kernel/setup.c > @@ -296,8 +296,8 @@ void __init setup_arch(char **cmdline_p) > setup_smp(); > #endif > > - riscv_fill_hwcap(); > riscv_init_cbom_blocksize(); > + riscv_fill_hwcap(); > apply_boot_alternatives(); > } > > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c > index cd2225304c82..8a49ea5ba01d 100644 > --- a/arch/riscv/mm/dma-noncoherent.c > +++ b/arch/riscv/mm/dma-noncoherent.c > @@ -12,7 +12,7 @@ > #include <linux/of_device.h> > #include <asm/cacheflush.h> > > -static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES; > +static unsigned int riscv_cbom_block_size; > static bool noncoherent_supported; > > void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, > @@ -79,38 +79,41 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, > void riscv_init_cbom_blocksize(void) > { > struct device_node *node; > + unsigned long cbom_hartid; > + u32 val, probed_block_size; > int ret; > - u32 val; > > + probed_block_size = 0; > for_each_of_cpu_node(node) { > unsigned long hartid; > - int cbom_hartid; > > ret = riscv_of_processor_hartid(node, &hartid); > if (ret) > continue; > > - if (hartid < 0) > - continue; > - > /* set block-size for cbom extension if available */ > ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); > if (ret) > continue; > > - if (!riscv_cbom_block_size) { > - riscv_cbom_block_size = val; > + if (!probed_block_size) { > + probed_block_size = val; > cbom_hartid = hartid; > } else { > - if (riscv_cbom_block_size != val) > - pr_warn("cbom-block-size mismatched between harts %d and %lu\n", > + if (probed_block_size != val) > + pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", > cbom_hartid, hartid); > } > } > + > + if (probed_block_size) > + riscv_cbom_block_size = probed_block_size; > } > #endif > > void riscv_noncoherent_supported(void) > { > + WARN(!riscv_cbom_block_size, > + "Non-coherent DMA support enabled without a block size\n"); > noncoherent_supported = true; > } > -- > 2.37.2 >
On 06/09/2022 07:38, Andrew Jones wrote: > > Darn, of course this doesn't compile independently of Anup's move change. > I should have done the move first as Heiko suggested. > > I'll try again by posting both Anup's move change and this patch > rebased on Anup's. Should prob mark the patches as v3 when you do
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 202c83f677b2..96648c176f37 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -37,6 +37,7 @@ static bool errata_probe_cmo(unsigned int stage, if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return false; + riscv_cbom_block_size = L1_CACHE_BYTES; riscv_noncoherent_supported(); return true; #else diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 95ef6e2bf45c..2dfc463b86bb 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -296,8 +296,8 @@ void __init setup_arch(char **cmdline_p) setup_smp(); #endif - riscv_fill_hwcap(); riscv_init_cbom_blocksize(); + riscv_fill_hwcap(); apply_boot_alternatives(); } diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index cd2225304c82..8a49ea5ba01d 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -12,7 +12,7 @@ #include <linux/of_device.h> #include <asm/cacheflush.h> -static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES; +static unsigned int riscv_cbom_block_size; static bool noncoherent_supported; void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, @@ -79,38 +79,41 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, void riscv_init_cbom_blocksize(void) { struct device_node *node; + unsigned long cbom_hartid; + u32 val, probed_block_size; int ret; - u32 val; + probed_block_size = 0; for_each_of_cpu_node(node) { unsigned long hartid; - int cbom_hartid; ret = riscv_of_processor_hartid(node, &hartid); if (ret) continue; - if (hartid < 0) - continue; - /* set block-size for cbom extension if available */ ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); if (ret) continue; - if (!riscv_cbom_block_size) { - riscv_cbom_block_size = val; + if (!probed_block_size) { + probed_block_size = val; cbom_hartid = hartid; } else { - if (riscv_cbom_block_size != val) - pr_warn("cbom-block-size mismatched between harts %d and %lu\n", + if (probed_block_size != val) + pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", cbom_hartid, hartid); } } + + if (probed_block_size) + riscv_cbom_block_size = probed_block_size; } #endif void riscv_noncoherent_supported(void) { + WARN(!riscv_cbom_block_size, + "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; }