| Message ID | 20220906124747.1767318-1-benedikt.niedermayr@siemens.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | omap-gpmc wait pin additions | expand |
From: Benedikt Niedermayr <benedikt.niedermayr@siemens.com>
Currently it is not possible to configure the WAIT0PINPOLARITY and
WAIT1PINPOLARITY bits of the GPMC_CONFIG register directly via
device tree properties.
It is also not possible to use the same wait-pin for different
cs-regions.
While the current implementation may fullfill most usecases, it may not
be sufficient for more complex setups (e.g. FPGA/ASIC interfaces), where
more complex interfacing options where possible.
For example interfacing an ASIC which offers multiple cs-regions but
only one waitpin the current driver and dt-bindings are not sufficient.
While using the same waitpin for different cs-regions worked for older
kernels (4.14) the omap-gpmc.c driver refused to probe (-EBUSY) with
newer kernels (>5.10).
Changes since v1:
* Rebase against recent 6.0.0-rc3 kernel, but the maintainers list
stays the same!
* Updated eMail recipients list
* Remove the gpmc register configuration out of the gpiochip
callbacks. In this case the memory interface configuration
is not done via gpio bindings.
* Some minor code fixes
* Changed git commit descriptions
Benedikt Niedermayr (3):
memory: omap-gpmc: allow shared wait pins
memory: omap-gpmc: add support for wait pin polarity
dt-bindings: memory-controllers: gpmc-child: add wait-pin polarity
.../memory-controllers/ti,gpmc-child.yaml | 6 ++++
drivers/memory/omap-gpmc.c | 36 +++++++++++++++----
include/linux/platform_data/gpmc-omap.h | 1 +
3 files changed, 36 insertions(+), 7 deletions(-)
On 06/09/2022 14:47, B. Niedermayr wrote: > From: Benedikt Niedermayr <benedikt.niedermayr@siemens.com> > > Currently it is not possible to configure the WAIT0PINPOLARITY and > WAIT1PINPOLARITY bits of the GPMC_CONFIG register directly via > device tree properties. > Just a disclaimer: This waits in my inbox for a week, it's not ignored. Unfortunately it will need to wait a bit more, due to traveling / ELCE. I see some discussion going, though. Best regards, Krzysztof
From: Benedikt Niedermayr <benedikt.niedermayr@siemens.com> Currently it is not possible to configure the WAIT0PINPOLARITY and WAIT1PINPOLARITY bits of the GPMC_CONFIG register directly via device tree properties. It is also not possible to use the same wait-pin for different cs-regions. While the current implementation may fullfill most usecases, it may not be sufficient for more complex setups (e.g. FPGA/ASIC interfaces), where more complex interfacing options where possible. For example interfacing an ASIC which offers multiple cs-regions but only one waitpin the current driver and dt-bindings are not sufficient. While using the same waitpin for different cs-regions worked for older kernels (4.14) the omap-gpmc.c driver refused to probe (-EBUSY) with newer kernels (>5.10). Changes since v1: * Rebase against recent 6.0.0-rc3 kernel, but the maintainers list stays the same! * Updated eMail recipients list * Remove the gpmc register configuration out of the gpiochip callbacks. In this case the memory interface configuration is not done via gpio bindings. * Some minor code fixes * Changed git commit descriptions Benedikt Niedermayr (3): memory: omap-gpmc: allow shared wait pins memory: omap-gpmc: add support for wait pin polarity dt-bindings: memory-controllers: gpmc-child: add wait-pin polarity .../memory-controllers/ti,gpmc-child.yaml | 6 +++++ drivers/memory/omap-gpmc.c | 23 +++++++++++++++++-- include/linux/platform_data/gpmc-omap.h | 1 + 3 files changed, 28 insertions(+), 2 deletions(-)