| Message ID | 20220906125523.38765-1-victor.colombo@eldorado.org.br (mailing list archive) |
|---|---|
| Headers | show |
| Series | Multiple ppc instructions fixes | expand |
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 9/6/22 09:55, Víctor Colombo wrote: > This patch set fixes multiple instructions for PPC targets that were > producing incorrect results, or setting the wrong bits in FPSCR. > > Patch 1 is just a style fix, trivial. > Patch 8 adds helper_reset_fpstatus() calls to instructions > that have an issue where the exception flags are being kept from > the previous instruction, causing incorrect bits to be set, > specially the non-sticky FI bit. > Other patches fixes other specific situations. > > v1->v2: > - Squash patches 8 through 19 and write a better commit message to it. > - Dropped Daniel's R-b in the squashed patches, as the squash merged > both reviewed and non-reviewed patches. Now require a new, single > R-b. > > Víctor Colombo (8): > target/ppc: Remove extra space from s128 field in ppc_vsr_t > target/ppc: Remove unused xer_* macros > target/ppc: Zero second doubleword in DFP instructions > target/ppc: Set result to QNaN for DENBCD when VXCVI occurs > target/ppc: Zero second doubleword for VSX madd instructions > target/ppc: Set OV32 when OV is set > target/ppc: Zero second doubleword of VSR registers for FPR insns > target/ppc: Clear fpstatus flags on helpers missing it > > target/ppc/cpu.h | 6 +----- > target/ppc/dfp_helper.c | 31 ++++++++++++++++++++++++++++--- > target/ppc/fpu_helper.c | 39 +++++++++++++++++++++++++++------------ > target/ppc/int_helper.c | 4 ++-- > target/ppc/translate.c | 8 ++++++++ > 5 files changed, 66 insertions(+), 22 deletions(-) >
This patch set fixes multiple instructions for PPC targets that were producing incorrect results, or setting the wrong bits in FPSCR. Patch 1 is just a style fix, trivial. Patch 8 adds helper_reset_fpstatus() calls to instructions that have an issue where the exception flags are being kept from the previous instruction, causing incorrect bits to be set, specially the non-sticky FI bit. Other patches fixes other specific situations. v1->v2: - Squash patches 8 through 19 and write a better commit message to it. - Dropped Daniel's R-b in the squashed patches, as the squash merged both reviewed and non-reviewed patches. Now require a new, single R-b. Víctor Colombo (8): target/ppc: Remove extra space from s128 field in ppc_vsr_t target/ppc: Remove unused xer_* macros target/ppc: Zero second doubleword in DFP instructions target/ppc: Set result to QNaN for DENBCD when VXCVI occurs target/ppc: Zero second doubleword for VSX madd instructions target/ppc: Set OV32 when OV is set target/ppc: Zero second doubleword of VSR registers for FPR insns target/ppc: Clear fpstatus flags on helpers missing it target/ppc/cpu.h | 6 +----- target/ppc/dfp_helper.c | 31 ++++++++++++++++++++++++++++--- target/ppc/fpu_helper.c | 39 +++++++++++++++++++++++++++------------ target/ppc/int_helper.c | 4 ++-- target/ppc/translate.c | 8 ++++++++ 5 files changed, 66 insertions(+), 22 deletions(-)